Chapter 12: TRACE

R

In the following figure, the clock skew Tsk is the delay from the clock input (CLKIOB) to

Table 12-2:Clock Skew and Setup Checking Terminology

Terms

Definition

 

 

constraint

The required time interval for the path, either specified explicitly by you

 

with a FROM TO constraint, or derived from a PERIOD constraint.

 

 

Tpath

The summation of component and connection delays along the path.

 

 

Tsu (setup)

The setup requirement for the destination register.

 

 

Tsk (skew)

The difference between the arrival time for the destination register and

 

the source register.

 

 

Slack

The negative slack shows that a setup error may occur, because the data

 

from the source register does not set up at the target register for a

 

subsequent clock edge.

 

 

register D (TclkD) less the delay from the clock input (CLKIOB) to register S (TclkS). Negative skew relative to the destination reduces the amount of time available for the data path, while positive skew relative to the destination register increases the amount of time available for the data path.

S

CLKIOB

Interconnect

and Logic

D

X8260

Figure 12-2:Clock Skew Example

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Xilinx 8.2i manual 2Clock Skew and Setup Checking Terminology Terms Definition, 2Clock Skew Example
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8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

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