Xilinx 8.2i manual 3Clock Passing Through Multiple Buffers

R

TRACE Reports

Because the total clock path delay determines the clock arrival times at the source register (TclkS) and the destination register (TclkD), this check still applies if the source and destination clocks originate at the same chip input but travel through different clock buffers and routing resources, as shown in the following figure.

FIFO UP/DOWN COUNTER

RESET

BUFCTR_CE

BUFCTR_UPDN

C

RESET

CE

Q

UP/DN

C

X8261

C

DIN

WE

RE

DOUT

FULL

EMPTY

Figure 12-3:Clock Passing Through Multiple Buffers

When the source and destination clocks originate at different chip inputs, no obvious relationship between the two clock inputs exists for TRACE (because the software cannot determine the clock arrival time or phase information).

For FROM TO constraints, TRACE assumes you have taken into account the external timing relationship between the chip inputs. TRACE assumes both clock inputs arrive simultaneously. The difference between the destination clock arrival time (TclkD) and the source clock arrival time (TclkS) does not account for any difference in the arrival times at the two different clock inputs to the chip, as shown in the following figure.

X DO DI X X X X

X X DO DI X X X

X8262

Figure 12-4:Clocks Originating at Different Device Inputs

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