Place and Route Report File

Chapter 9: PAR

As the command is performed, PAR records a summary of all placement and routing iterations in one PAR file at the same level as the directory you specified, then places the output files (in NCD format) in the specified directory. Also, a Place and Route Report File and a PAD file are created for each NCD file, describing in detail each individual iteration.

Note: Reports are formatted for viewing in a monospace (non-proportional) font. If the text editor you use for viewing the report uses a proportional font, the columns in the report do not line up correctly. The pad.csv report is formatted for importing into a spreadsheet program or for parsing via a user script.

The Place and Route report file contains execution information about the PAR command run. The report file shows the steps taken as the program converges on a placement and routing solution. A sample PAR report file follows:

The first lines of the PAR report identify the software version you are running, the machine on which it is run, and the date and time stamp. In addition, the command line entry is restated, along with information about the input design files (NCD and PCF). Warning messages also appear in the first section of the PAR report.

Release 8.1i - par HEAD

Par –w –ol high c:\test\test_top_mod_map.ncd c:\test\par0.ncd c:\test\test_top_mod.pcf

Constraints file: c:\test\test_top_mod.pcf.

Loading device for application Rf_Device from file ‘2vp2.nph’ in envi- ronment c:/Xilinx.

"test_top_mod" is an NCD, version 1.0, device xc2vp2, package ff672, speed -7

Initializing temperature to 100.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)

Initializing voltage to 1.500 Volts. (default - Range: 1.400 to 1.600 Volts)

WARNING:Timing:2796 - The input clock clkB_IBUFG to DCM test_lutram_bram/test_DCM has a period (frequency) specification of 2700 ps (370.37 Mhz). This violates the minimum period (maximum fre- quency) of 4761 ps (210.04 Mhz).

WARNING:Timing:2798 - The output clock test_lutram_bram/CLK0_W from DCM test_lutram_bram/test_DCM has a period (frequency) specification of 2700 ps (370.37 Mhz). This violates the minimum period (maximum fre- quency) of 4761 ps (210.04 Mhz).

The next section of the PAR report provides a breakdown of the resources in the design and includes the Device Utilization Summary.

Device speed data version: "PRODUCTION 1.90 2005-12-13".

Device Utilization Summary:
Number of BUFGMUXs		4	out of 16			25%
Number of	DCMs	1	out	of	4	25%
Number of	External IOBs	80	out	of	204	39%

174

www.xilinx.com

Development System Reference Guide

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Xilinx 8.2i manual Place and Route Report File

Models: 8.2i

Chapter 9: PAR