R

MAP Process

•The aggressive setting transforms the entire bus.

♦Buses A, B have the same result as the on setting.

♦Bus C is implemented entirely by CY chain. (30 ≤ the default upper limit for carry chain transformation)

•The limit setting is the most conservative. It transforms only that portion of the number of CLB(s) or BUFT(s) per row in a device.

Note: The –txoption is not used for devices that do not have TBUFs, which include Virtex-4,

Spartan-3, and Spartan-3E device families.

–u (Do Not Remove Unused Logic)

By default (without the –u option), MAP eliminates unused components and nets from the design before mapping. If –u is specified, MAP maps unused components and nets in the input design and includes them as part of the output design.

The –u option is helpful if you want to run a preliminary mapping on an unfinished design, possibly to see how many components the mapped design uses. By specifying –u, you are assured that all of the design’s logic (even logic that is part of incomplete nets) is mapped.

–xe (Extra Effort Level)

–xeeffort_level

The –xe option is available when running timing-driven packing and placement with the –timing option. The –xe option sets the extra effort level. The effort_level variable can be set to n (normal) or c (continue). Extra effort c allows you to direct MAP to continue packing. MAP continues to attempt to improve packing until little or no improvement can be made.

map –ol high –xe n design.ncd output.ncd design.pcf

MAP Process

MAP performs the following steps when mapping a design.

1.Selects the target Xilinx device, package, and speed. MAP selects a part in one of the following ways:

♦Uses the part specified on the MAP command line.

♦If a part is not specified on the command line, MAP selects the part specified in the input NGD file. If the information in the input NGD file does not specify a complete architecture, device, and package, MAP issues an error message and stops. If necessary, MAP supplies a default speed.

2.Reads the information in the input design file.

3.Performs a Logical DRC (Design Rule Check) on the input design. If any DRC errors are detected, the MAP run is aborted. If any DRC warnings are detected, the warnings are reported, but MAP continues to run. The Logical DRC (also called the NGD DRC) is described in Chapter 5, “Logical Design Rule Check”.

Note: Step 3 is skipped if the NGDBuild DRC was successful.

Development System Reference Guide

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Xilinx 8.2i manual MAP Process, Do Not Remove Unused Logic, Xe Extra Effort Level, Xeeffortlevel
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8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.
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