Xilinx 8.2i manual PIN2UCF Syntax, PIN2UCF Input Files, PIN2UCF Output Files

Models: 8.2i

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PIN2UCF Syntax

PIN2UCF writes to an existing UCF under the following conditions:

The contents in the PINLOCK section are all pin lock matches, and there are no conflicts between the PINLOCK section and the rest of the UCF.

The PINLOCK section contents are all comments and there are no conflicts outside of the PINLOCK section.

There is no PINLOCK section and no other conflicts in the UCF.

Note: Comments inside an existing PINLOCK section are never preserved by a new run of PIN2UCF. If PIN2UCF finds a CSTTRANS comment, it equates “INST name” to “NET name” and then checks for comments.

PIN2UCF Syntax

The following command runs the PIN2UCF command line program:

pin2ucf {ncd_file.ncdpin_freeze_file.gyd} [–rreport_file_name -ooutput.ucf]

ncd_file or pin_freeze_file is the name of the input placed and routed NCD file for FPGAs, or the fitted GYD file for CPLDs.

PIN2UCF Input Files

PIN2UCF uses the following files as input:

NCD file—The minimal requirement is a placed NCD file, but you would normally use a placed and routed NCD file that meets (or is fairly close to meeting) timing specifications.

GYD file—The PIN2UCF pin-locking utility replaces the old GYD file mechanism that was used by CPLDs to lock pins. The GYD file is still available as an input guide file to control pin-locking. Running PIN2UCF is the recommended method of pin-locking to be used instead of specifying the GYD file as a guide file.

PIN2UCF Output Files

PIN2UCF creates the following files as output:

UCF—If there is no existing UCF, PIN2UCF creates one. If an output.ucf file is not specified for PIN2UCF and a UCF with the same root name as the design exists in the same directory as the design file, the program writes to that file automatically unless there are constraint conflicts.

RPT file— A pinlock.rpt file is written to the current directory by default. Use the –r option to write a report file to another directory. See “–r (Write to a Report File)” for more information.

Development System Reference Guide

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Xilinx 8.2i manual PIN2UCF Syntax, PIN2UCF Input Files, PIN2UCF Output Files

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.