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Xilinx 8.2i manual Setfilter set filter for analysis, Setquery set up net or timegroup report

Models: 8.2i

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Tcl Commands for General Usage

set_filter (set filter for analysis)

The timing_analysis set_filter command sets a net filter to exclude or include the specified nets from a path analysis.

%timing_analysis set_filter <analysis_name> <filter_type> <filter_value> <filter_items>

timing_analysis is the name of the Xilinx Tcl command. set_filter is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

filter_type specifies the type of analysis filter. Supported filter types are net and timegroup. filter_value specifies the value for the filter type. Net filter values are include and exclude.

filter_items specifies the items to be filtered. For the net filter type, these are the names of nets in the current design.

Example:

% timing_analysis set_filter stopwatch_timing nets

 

exclude “ureg_net_1 ureg_net_2 ureg_net_3”

 

 

Description:

In this example, the specified nets are excluded from the

 

stopwatch_timing analysis. Note that the nets to exclude are entered

 

as text strings, which are distinguished by double quotes (“).

Tcl Return:

1 if the filter is set successfully; 0 otherwise.

set_query (set up net or timegroup report)

The timing_analysis set_query command sets up a report that shows net delays and fanouts, or blocks associated with timegroups.

%timing_analysis set_query <analysis_name> <query_type> <query_items>

timing_analysis is the name of the Xilinx Tcl command.

set_query is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

query_type specifies the type of query. Supported queries are:

net—generates a report that shows the delay details for the specified query items. timegroup—generates a report that shows blocks of the specified timegroups.

Development System Reference Guide

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Xilinx 8.2i Setfilter set filter for analysis, Setquery set up net or timegroup report, Exclude uregnet1 uregnet2 uregnet3
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8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.