Xilinx 8.2i manual 336

Chapter 22: NetGen

R

–module (Simulation of Active Module)

–module

The –module option creates a netlist file based on the active module, independent of the top-level design. NetGen constructs the netlist based only on the active module’s interface signals.

To use this option you must specify an NCD file that contains an expanded active module.

Note: The –module option is for use with the Modular Design flow.

–ne (No Name Escaping)

By default (without the –ne option), NetGen “escapes” illegal block or net names in your design by placing a leading backslash (\) before the name and appending a space at the end of the name. For example, the net name “p1$40/empty” becomes “\p1$40/empty” when name escaping is used. Illegal Verilog characters are reserved Verilog names, such as “input” and “output,” and any characters that do not conform to Verilog naming standards.

The –ne option replaces invalid characters with underscores, so that name escaping does not occur. For example, the net name “p1$40/empty” becomes “p1$40_empty” when name escaping is not used. The leading backslash does not appear as part of the identifier. The resulting Verilog file can be used if a vendor’s Verilog software cannot interpret escaped identifiers correctly.

–pcf (PCF File)

-pcf pcf_file.pcf

The –pcf option allows you to specify a PCF (physical constraints file) as input to NetGen. You only need to specify a constraints file if it contains prorating constraints (temperature or voltage).

Temperature and voltage constraints and prorated delays are described in the Constraints Guide.

–s (Change Speed)

–s[speed grade]

The –s option instructs NetGen to annotate the device speed grade you specify to the netlist. The device speed can be entered with or without the leading dash. For example, –s 3 or –s –3 can be used.

Some architectures support the –s min option. This option instructs NetGen to annotate a process minimum delay, rather than a maximum worst-case delay and relative minimum delay, to the netlist. The command line syntax is the following:

-s min

Minimum delay values may not be available for all device families. Use the Speedprint program or the PARTGen program to determine whether process minimum delays are available for your target architecture. See Chapter 13, “Speedprint” or Chapter 4, “PARTGen” for more information.

Note: Settings made with the –s min option override any prorated timing parameters in the PCF. If –s min is used then all fields (MIN:TYP:MAX) in the resulting SDF file are set to the process minimum value.

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