Inputs Number of Inputs to Use During Optimization

Chapter 18: CPLDfit

–inputs (Number of Inputs to Use During Optimization)

-inputs [limit:2,36]

The -inputs option specifies the maximum number of inputs for a single equation. The higher this value, the more resources a single equation may use, possibly limiting the number of equations allowed in a single function block. The maximum limit varies with each CPLD architecture. The limits are as follows (default in parentheses):

XC9500 = 36 (36)

XC9500XL/XV = 54 (54)

CoolRunner XPLA3 = 40 (36)

CoolRunner-II = 40 (36)

–iostd (Specify I/O Standard)

-iostd [LVTTLLVCMOS18LVCMOS25 SSTL2_ISSTL3_IHSTL_ILVCMOS15]

The -iostd option sets the default voltage standard for all I/Os. The default is overridden by explicit assignments. Not all I/O standards are available for each architecture. The available I/O standards follow (default in parentheses):

CoolRunner-II: LVTTL, LVCMOS18, LVCMOS25, SSTL2_I, SSTL3_I, HSTL_I, LVCMOS15, LVCMOS18

–keepio (Prevent Optimization of Unused Inputs)

The -keepio option prevents unused inputs from being optimized. By default, CPLDfit trims unconnected input pins.

Architecture Support: XC9500, XC9500XL/XV, CoolRunner XPLA3, CoolRunner-II

–loc (Keep Specified Location Constraints)

-loc [onofftry]

The -loc option specifies how CPLDfit uses the design location constraints. The on setting directs CPLDfit to obey location constraints. The off setting directs CPLDfit to ignore location constraints. The try setting directs CPLDfit to use location constraints unless doing so would result in a fitting failure. The default setting is on.

–localfbk (Use Local Feedback)

The XC9500 macrocell contains a local feedback path. The -localfbk option turns this feedback path on. This option is off by default.

Architecture Support: XC9500

–log (Specify Log File)

-loglogfile

The -log option generates a logfile that contains all error, warning, and informational messages.

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Development System Reference Guide

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

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The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

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In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Xilinx 8.2i manual Inputs Number of Inputs to Use During Optimization, Iostd Specify I/O Standard

Models: 8.2i