Xilinx 8.2i manual Mppr Multi-Pass Place and Route for FPGAs

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XFLOW Flow Types

–mppr (Multi-Pass Place and Route for FPGAs)

–mpproption_file

This flow type runs multiple place and route passes on your FPGA design. It invokes the fpga.flw flow file and runs NGDBuild, MAP, multiple PAR passes, and TRACE. After running the multiple PAR passes, XFLOW saves the “best” NCD file in the subdirectory called mppr.dir. (Do not change the name of this default directory.) This NCD file uses the naming convention placer_level_router_level_cost_table.ncd.

XFLOW then copies this “best” result to the working directory and renames it

design_name.ncd. It also copies the relevant DLY, PAD, PAR, and XPI files to the working directory.

Note: By default, XFLOW does not support the multiple-node feature of the PAR Turns Engine. If you want to take advantage of this UNIX-specific feature, you can modify the appropriate option file to include the PAR –m option. See “–m(Multi-Tasking Mode)” in Chapter 9 for more information.

Xilinx provides the following option files for use with this flow type. These files allow you to set how exhaustively PAR attempts to place and route your design.

Note: Each place and route iteration uses a different “cost table” to create a different NCD file. There are 100 cost tables numbered 1 through 100. Each cost table assigns weighted values to relevant factors such as constraints, length of connection, and available routing resources.

Table 23-10:Option Files for –mppr Flow Type

Option Files	Description
overnight.opt	Runs 10 place and route iterations
weekend.opt	Runs place and route iterations until
	the design is fully routed or until 100
	iterations are complete
exhaustive.opt	Runs 100 place and route iterations

The following example shows how to use the -mppr flow type:

xflow –p xc2v250fg256-5 –mppr overnight.opt testclk.edf

–sta (Create a File for Static Timing Analysis)

–staoption_file

This flow type generates a file that can be used to perform static timing analysis of an FPGA design. It invokes the fpga.flw flow file and runs NGDBuild and NetGen to generate a Verilog netlist compatible with supported static timing analysis tools.

Xilinx provides the following option file for use with this flow type.

Table 23-11:Option Files for –sta Flow Type

Option File	Description
primetime_verilog.opt	Option file for static timing analysis of
	Primetime.

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