Chapter 3: Tcl

R

reset (reset path filters and constraints)

The timing_analysis reset command resets all existing path filters and custom constraints for the analysis.

% timing_analysis reset <analysis_name>

timing_analysis is the name of the Xilinx Tcl command.

reset is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

Example:

% timing_analysis reset stopwatch_timing

 

 

Description:

In this example, the timing_analysis reset command is used to reset all

 

of the path filters and any custom constraints in the stopwatch_timing

 

analysis.

Tcl Return:

True if all path filters were cleared successfully, false otherwise.

run (run analysis)

The timing_analysis run command executes an analysis and returns the name of the timing, net, or timegroup report file. The analysis is based on the property settings assigned with the timing_analysis set command. An analysis is first created with the timing_analysis new command. See “set (set analysis properties)” and “new (new timing analysis)” for more information.

% timing_analysis run <analysis_name>

timing_analysis is the name of the Xilinx Tcl command.

run is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

Example:

% timing_analysis run stopwatch_timing

 

 

Description:

In this example, the timing_analysis run command is used to execute a

 

timing analysis and create a new analysis report.

Tcl Return:

Name of the timing analysis.

saveas (save analysis report)

The timing_analysis saveas command saves the analysis to a specified file.

%timing_analysis saveas <analysis_name> <new_file_name>

timing_analysis is the name of the Xilinx Tcl command.

saveas is the name of the timing_analysis subcommand.

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Development System Reference Guide

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Xilinx 8.2i manual Reset reset path filters and constraints, Run run analysis, Saveas save analysis report
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8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.
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