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Xilinx 8.2i manual Tcl 10 PAR Options

Models: 8.2i

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Chapter 3: Tcl

Table 3-10: PAR Options

Option Name	Implementation Tool

“Extra Effort (Highest PAR level only)”	PAR

“Generate Asynchronous Delay Report”	PAR

“Generate Clock Region Report”	PAR

“Generate Post-Place & Route Simulation Model”	PAR

“Generate Post-Place & Route Static Timing Report”	PAR

“Nodelist File (Unix Only)”	PAR

“Number of PAR Iterations (1-100)”	PAR

“Number of Results to Save (0-100)”	PAR

“Other Place & Route Command Line Options”	PAR

“PAR Guide Design File (.ncd)”	PAR

“PAR Guide Mode”	PAR

“Place & Route Effort Level (Overall)”	PAR

“Place and Route Mode”	PAR

“Place Effort Level (Overrides Overall Level)”	PAR

“Power Reduction”	PAR

“Router Effort Level (Overrides Overall Level)”	PAR

“Save Results in Directory (.dir will be appended)”	PAR

“Starting Placer Cost Table (1-100)”	PAR

“Use Bonded I/Os”	PAR

“Using Timing Constraints”	PAR

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Development System Reference Guide

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8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Contents

Development System Reference Guide Development System Reference Guide Guide Contents About This GuidePreface About This Guide Additional Resources ConventionsTypographical Online Document Preface About This Guide Convention Meaning or Use ExampleAllow block blockname Loc1 loc2 ... locnTable of Contents Tcl PARTGen Logical Design Rule Check NGDBuildMAP Physical Design Rule Check PARDevelopment System Reference Guide XPower PIN2UCFTrace Trace Output FilesSpeedprint BitGenBSDLAnno PROMGen IBISWriterCPLDfit TsimTAEngine Hprep6 NetGenDevelopment System Reference Guide Xflow Data2MEM EDIF2NGD, and NGDBuildCommand Line Program Overview 1Command Line Programs in the Design Flow Design Flow StepIntroduction Command Line Syntax Command Line OptionsExecute Commands File IntroductionCommand Line Options Symbol DescriptionHelp Introduction Symbol Description Intstyle Integration StyleProgramname -harchitecturename Programname -h filename2Part Number Examples Specification Part NumberInvoking Command Line Programs Introduction 2Part Number Examples SpecificationDesign Flow Design Flow OverviewDesign Flow Xilinx Design FlowDesign Flow Overview 2Xilinx Software Design Flow FPGAs3Xilinx Software Design Flow CPLDs Design Entry and Synthesis Hierarchical DesignDesign Entry and Synthesis Schematic Entry Overview Library ElementsCore Generator Tool FPGAs Only HDL Entry and Synthesis Functional SimulationConstraints Mapping Constraints FPGAs OnlyBlock Placement Timing SpecificationsDesign Implementation Netlist Translation ProgramsDesign Implementation 5Design Implementation Flow FPGAs6Design Implementation Flow CPLDs Mapping FPGAs Only Placing and Routing FPGAs OnlyBitstream Generation FPGAs Only Design Verification 1Verification Tools Verification TypeDesign Verification 7Three Verification Methods of the Design Flow FPGAsSimulation Back-Annotation9Back-Annotation Flow for FPGAs Schematic-Based Simulation NetGenHDL-Based Simulation Timing Simulation11Simulation Points for HDL Designs 2Five Simulation Points in HDL Design Flow UniSim SimPrimStatic Timing Analysis FPGAs Only In-Circuit Verification Design Rule Checker FPGAs OnlyXilinx Design Download Cables Probe3Global Clock Resources Fpga Family Number Destination Pins Fpga Design TipsDesign Size and Performance Global Clock DistributionData Feedback and Clock Enable 12 Gated Clock13Synchronous Design Using Data Feedback CountersOther Synchronous Design Considerations Q0. . . .Q7 Q8. . . .Q15Q0. . . .Q7Q8. . . .Q15 Tcl Tcl OverviewAccessing Help Xilinx Tcl ShellTcl Fundamentals Tcl FundamentalsXilinx Tcl Commands 1Xilinx Tcl Commands for General Usage SubcommandsXilinx Namespace Project create and manage projects Tcl Commands for General Usage 2Xilinx Tcl Commands for Advanced Scripting SubcommandsPartition support design preservation Tcl Commands for General Usage Delete delete a partitionGet get partition properties Partition delete /stopwatch/Instdcm1New create a new partition Partition get /stopwatch/Instdcm1 preservePartition new /stopwatch/Instdcm1 Properties list available partition properties Rerun force partition synthesis and implementationPartition properties Set set partition preserve property Process run and manage project processes Run run process task4Process Tasks Clean remove system-generated project files Project cleanProject create and manage projects Close close the ISE project Get get project propertiesGetprocesses get project processes Project closeNew create a new ISE project Open open an ISE projectProject getprocesses -instance Instdcm1 Project new watchver.iseProperties list project properties Set set project properties, values, and optionsProject properties -process all Set device set device Set family set device familyProject set Map Effort Level high Project set device xc2vp2Set package set device package Set speed set device speedProject set family Virtex2p Project set package fg256Timinganalysis generate timing analysis reports Set top set the top-level module/entityDelete delete timing analysis Project set speedDisableconstraints disable timing constraints Disablecpt disable components for path tracing controlEnablecpt enable components for path tracing control Timinganalysis enableconstraintsStopwatchtiming TSclk=PERIOD TIMEGROUP\sclk\ Ns High 50.00000%Timinganalysis enablecpt stopwatchtiming Get get analysis propertyRegsrclk ureg1 ureg2 ureg3 Ascii New new timing analysis Reset reset path filters and constraints Timinganalysis reset stopwatchtimingRun run analysis Saveas save analysis reportSet set analysis properties Setconstraint set constraint for custom analysisTiminganalysis set stopwatchtiming AnalysisspeedSetendpoints set source and destination endpoints Timinganalysis setconstraint stopwatchtimingPeriod 13 sclk Setquery set up net or timegroup report Setfilter set filter for analysisTiminganalysis setfilter stopwatchtiming nets Exclude uregnet1 uregnet2 uregnet3Showsettings generate settings report Xfile manage project filesAdd add file to project ExampleGet get project file properties Remove remove file from projectXfile add *.vhd /mysource/mysubdir timing.ucf Xfile get timestamp stopwatch.vhdTcl Commands for Advanced Scripting Collection create and manage a collectionAppendto add objects to a collection Xfile remove stopwatch.vhdTcl Commands for Advanced Scripting Copy copy a collectionSet colVar1 search * -type instance Set colVar2 $colVar1Equal compare two collections Set colVar2 collection copy $colVar1Set colVar2 search /top/T* -type instance Collection equal $colVar1 $colVar2Foreach iterate over elements in a collection Get get collection propertyIndex extract a collection object Properties list available collection propertiesSet item collection index $colVar Object name $itemRemovefrom remove objects from a collection Set set the property for all collectionsCollection properties Object get object information Sizeof show the number of objects in a collectionCollection set displaytype true Collection sizeof $colVarGet get object properties Name name of the objectCollection foreach obj $colVar set objProps Object properties $obj foreach prop $objPropsProperties list object properties Object name collection index $colVarSet colVar search * -type partition Search search and return matching objects Type type of objectObject type collection index $colVar Project Properties and Options Search /stopwatch -type instance6Project Properties Property Name Description Option Name Synthesis ToolProject Properties and Options NGDBuild Options Option Name Implementation Tool Option Name Implementation Tool Tcl 10 PAR Options Example Tcl Scripts Sample Tcl Script for General UsageExample Tcl Scripts Tcl Sample Tcl Script for Advanced Scripting 100 PARTGen PARTGen OverviewPARTGen Syntax Partgen optionsPARTGen Input Files PARTGen Output FilesPARTGen Options Arch Print Information for Specified ArchitecturePARTGen Options Print a List of Devices, Packages, and Speeds PARTGen Options 2s400e Creates Package file and Partlist Files Nopkgfile No Package FilePname Xcv400 Device V400bg432 PartPartlist File Creates Package and Partlist FilesHeader Device AttributesPartlist File Part architecture family partname diename packagefilenameSelect RAM PKG File PKG FileDone Logical Design Rule Check Logical DRC OverviewLogical DRC Checks Block CheckNet Check Pad CheckClock Buffer Check Name CheckLogical DRC Checks 1Checked Primitive Pins NGD Primitive Pins Checked Primitive Pin CheckNGDBuild NGDBuild OverviewConverting a Netlist to an NGD File 1NGDBuild Design FlowNGDBuild Syntax NGDBuild Input FilesNGDBuild Syntax Ngdbuild options designname ngdfile.ngd120 Add PADs to Top-Level Port Signals NGDBuild Output FilesNGDBuild Intermediate Files NGDBuild OptionsAul Allow Unmatched LOCs Bm Specify BMM FilesDd Destination Directory Ignore UCF FileInsertkeephierarchy Libraries to SearchNGDBuild Options SynopsysModular assemble Module Assembly Modular initial Initial Budgeting of Modular DesignModular assemble -pimpath pimdirectorypath Usepimmodulename1 -usepimmodulename2Modular module Active Module Implementation Nt Netlist Translation TypeModular module -active modulename Pimcreate pimdirectory -ncd designnamerouted.ncdIgnore LOC Constraints Sd Search Specified DirectoryAllow Unexpanded Blocks Uc User Constraints File Ur Read User Rules FileVerbose Report All Messages Uc ucffile.ucf128 MAP MAP OverviewMAP Syntax Map options infile.ngd pcffile.pcfMAP Input Files MAP Output FilesMAP Input Files MAP Options 1Map Options and ArchitecturesBp Map Slice Logic Pack CLBsMAP Options 1Map Options and Architectures CpackfactorCm Cover Mode Detail Write Out Detailed MAP ReportEquivalentregisterremoval Remove Redundant Registers Cm area speed balancedGm Guide Mode Gm incremental Guide Mode incrementalGf Guide NCD File Globalopt Global OptimizationIgnorekeephierarchy Ignore Keephierarchy Properties Ir Do Not Use RLOCs to Generate RPMsIse ISE Project File Map to Input FunctionsNo logic replication Output File NameOl Overall Effort Level OlstdmedhighPr Pack Registers in I/O No Register OrderingRegisterduplication Duplicate Registers Retiming Register Retiming During Global OptimizationTiming Timing-Driven Packing and Placement Tx Transform BusesTx on off aggressive limit MAP Process Do Not Remove Unused LogicXe Extra Effort Level MAP ProcessRegister Ordering Register Ordering Data01 Addr02 Atod03 Dtoa04Guided Mapping 3Guided MappingSimulating Map Results Simulating Map Results4Logical Circuit Representation MAP Report MRP File MAP Report MRP File148 Development System Reference Guide 149 Type Block GND Xstgnd IOB 152 Halting MAP Halting MAP154 Physical Design Rule Check DRC OverviewDRC Syntax DRC Input FileDRC Output File DRC OptionsDRC Checks Report Incomplete ProgrammingDRC Checks DRC Errors and Warnings PAR Place and Route OverviewPAR Flow PAR Process PlacingRouting Timing-driven PARCommand Line Examples Par input.ncd output.ncdPar -k previous.ncd reentrant.ncd pref.pcf Guided PAR Guided PARPCI Cores PAR Syntax PAR Input FilesPAR Output Files PAR Syntax1Effort Level Options Function Range Default General Options Function Range DefaultPAR Options Ol value for the routerPAR Options 2General Options Function Range Default Guide Options Function Range DefaultExistingfile Execute Commands File Detailed Listing of OptionsGf Guide NCD File Gm Guide Mode Intstyle Integration StyleRe-Entrant Routing PAR OptionsMulti-Tasking Mode Number of PAR IterationsNopad No Pad Ol Overall Effort LevelNo Placement Power Power Aware PARPl Placer Effort Level No RoutingNumber of Results to Save Starting Placer Cost TableUb Use Bonded I/Os Overwrite Existing FilesPerformance Evaluation Mode PAR ReportsXe Extra Effort Level PAR ReportsPlace and Route Report File Development System Reference Guide 175 Ing score in parenthesis Development System Reference Guide 177 Multi Pass Place and Route Mppr Placer effort levelrouter effort levelcost table numberPar -n 3 -pl high -rl std address.ncd output.dir Select I/O Utilization and Usage Summary Importing the PAD File InformationGuide Reporting Multi Pass Place and Route MpprBest Performance Mode XplorerTiming Closure Mode Xplorer SyntaxXplorer Xplorer Input Files Xplorer Output FilesXplorer Options 5Xplorer Options FunctionXplorer Report Xplorer 5Xplorer Options Function184 ReportGen ReportGen SyntaxReportGen Input Files ReportGen Output FilesReportGen Options Option Usage FunctionIsexflowsilent Padfmt padcsvtxtTurns Engine PAR Multi-Tasking Option Turns Engine OverviewTurns Engine PAR Multi-Tasking Option Par -m nodefilename -ol high -n 10 mydesign.ncd output.dirTurns Engine Syntax Turns Engine Input FilesTurns Engine Output Files LimitationsSystem Requirements Turns Engine Environment Variables Debugging Rsh machinenameScreen Output Node Status JOB Time Halting PAR Halting PAR 196 XPower XPower OverviewXPower Syntax Files Used by XPowerFpga Designs Cpld DesignsUsing XPower Using XPowerVCD Data Entry Rename Power Report Other Methods of Data EntryLimit Ls List Supported DevicesSpecify Settings XML Input File Specify VCD fileTb Turn On Time Based Reporting Wx Write XML FileCommand Line Examples Power ReportsStandard Reports Power Reports Detailed ReportsAdvanced Reports 204 PIN2UCF PIN2UCF OverviewPIN2UCF Flow PIN2UCF Syntax PIN2UCF Input FilesPIN2UCF Output Files PIN2UCF SyntaxPIN2UCF Options PIN2UCF ScenariosWrite to a Report File Outfile.ucfExisting Pinlock section. 210 Trace Trace OverviewTrace Syntax Trace Input FilesTrce options design.ncd constraint.pcf Trce -runmacro.xtm design.ncd constraint.pcfTrace Output Files Input files to TraceTrace Output Files Generate an Error Report Trace OptionsAdvanced Analysis Fastpaths Report Fastest PathsNodatasheet No Data Sheet Limit Timing ReportOutput Timing Report File Name Trace OptionsRun Run Timing Analyzer Macro Change SpeedSkew Analyze Clock Skew for All Clocks SkewStamp Generates Stamp timing model files Report Uncovered PathsStampstampfile design.ncd UlimitTrace Command Line Examples Generate a Verbose ReportXml XML Output File Name VlimitTrace Reports Trace ReportsNet Delay Constraints Path Delay ConstraintsTiming Verification with Trace Net Skew ConstraintsClock Skew and Setup Checking 1Path Delay Constraint Terminology Definition2Clock Skew and Setup Checking Terminology Terms Definition 2Clock Skew Example3Clock Passing Through Multiple Buffers Reporting with Trace 5Error reporting for failed timing constraints Data Sheet Report Development System Reference Guide 227 BSLOT0 D0S Guaranteed Setup and Hold Reporting Report LegendSetup Times Hold TimesSummary Report Without a Physical Constraints File Specified Trce -o summary.twr ramb16s1.ncdTrce -o summary1.twr ramb16s1.ncd clkperiod.pcf Development System Reference Guide 233 Trce -e 3 ramb16s1.ncd clkperiod.pcf -o errorreport.twr Development System Reference Guide 235 236 Development System Reference Guide 237 BUFGMUX.I0 Offset Constraints Offset ConstraintsOffset in Constraint Examples Offset in HeaderOffset in Path Details Offset in Detailed Path Data Offset In with Phase Shifted Clock Offset in Detail Path Clock PathDevelopment System Reference Guide 243 Offset OUT Constraint Examples Offset OUT HeaderOffset OUT Path Details Offset OUT Detail Clock PathOffset OUT Detail Path Data Period Constraints Period Constraints ExamplesPeriod Header Period ConstraintsPeriod Path Period Path Details Period Constraint with Phase Period Path with Phase Halting Trace Minimum Period StatisticsSpeedprint Speedprint OverviewSpecify Temperature Speedprint SyntaxSpeedprint Options Min Display Minimum Speed DataSpeedprint Example Commands Speedprint Example CommandsCommand Description Speedprint Example ReportsLvttl Fast BitGen BitGen OverviewBitGen Syntax Option Output FileLoutfilename.ll Moutfilename.msk Boutfilename.rbt BitGen Input Files BitGen Output FilesBitGen Input Files BitGen Options Create Rawbits FileBd Update Block Rams Set ConfigurationBitgen -goptionsetting design.ncd design.bit design.pcf Do Not Run DRCActiveReconfig ActivateGCLKBinary CclkPinConfigRate CompressDCIUpdateMode DCMShutdownDebugBitstream DisableBandgap DONEcycleDonePin DonePipeDriveDone EncryptGclkdel0, Gclkdel1, Gclkdel2, Gclkdel3 GSRcycleGWEcycle GTScycleHswapenPin Key0, Key1, Key2, Key3, Key4, Key5KeyFile Keyseq0, Keyseq1, Keyseq2, Keyseq3, Keyseq4, Keyseq5LCKcycle M0PinM1Pin M2PinMatchcycle PartialGCLKPartialMask0, PartialMask1, PartialMask2 PartialLeftPartialRight PersistPowerdownPin ProgPinReadBack SecuritySEURepair StartCBCStartKey StartupClkTckPin TdiPinTdoPin TmsPinNo BIT File UnusedPinUserID Create a Logic Allocation File Generate a Mask FileCreate a Partial Bit File Overwrite Existing Output File276 BSDLAnno BSDLAnno OverviewBSDLAnno Syntax BSDLAnno Input FilesBSDLAnno Output Files BSDLAnno OptionsBSDLAnno File Composition Entity DeclarationGeneric Parameter BSDLAnno File CompositionLogical Port Description Package Pin-MappingUSE Statement Scan Port IdentificationTAP Description Bsdl File Modifications for Single-Ended Pins Boundary Register DescriptionExplanation Boundary Scan Behavior in Xilinx Devices Modifications to the Designwarning SectionHeader Comments BSDLAnno BSDLAnno version numberPROMGen PROMGen OverviewPROMGen Syntax PROMGen Input FilesPROMGen Output Files Promgen optionsPROMGen Options Add BIT FIles Prom FormatLoad Prom File File1.bit file2.bitProm Size Template FileLoad Upward Ver VersionEnable Compression Bit Swapping in Prom FilesPROMGen Examples PROMGen Examples292 IBISWriter IBISWriter OverviewIBISWriter Syntax Ibiswriter options infile outfile.ibsIBISWriter Input Files IBISWriter Output FilesIBISWriter Options Set Reference VoltageMl Multilingual Support Architecture Option Value DescriptionPin Generate Package Parasitics IBISWriter Options298 CPLDfit CPLDfit OverviewCPLDfit Syntax CPLDfit Input FilesCPLDfit Output Files CPLDfit Options Inputs Number of Inputs to Use During Optimization Iostd Specify I/O StandardKeepio Prevent Optimization of Unused Inputs Loc Keep Specified Location ConstraintsNofbnand Disable Use of Foldback Nands Nogclkopt Disable Global Clock OptimizationNogsropt Disable Global Set/Reset Optimization Nogtsopt Disable Global Output-Enable OptimizationPower Set Power Mode Optimize Optimize Logic for Density or SpeedSpecify Xilinx Part Pinfbk Use Pin FeedbackTerminate Set to Termination Mode Unused Set Termination Mode of Unused I/OsSlew Set Slew Rate Wysiwyg Do Not Perform Optimization306 Tsim Tsim SyntaxTsim Input Files TAEngine TAEngine OverviewTAEngine Syntax 1TAEngine Design FlowTAEngine Options Detail Detail ReportIopath Trace Paths Specify Output Filename312 Hprep6 1Hprep6 Design FlowHprep6 Syntax Hprep6 OptionsAutosig Automatically Generate Signature Nopullup Disable Pullups Specify Signature Value for ReadbackProduce ISC File Tmv Specify Test Vector File316 NetGen NetGen OverviewNetGen 1NetGen Output File Types Input Design FileNetGen Simulation Flow NetGen Functional Simulation FlowNetGen Supported Flows NetGen Simulation FlowNetGen Timing Simulation Flow Syntax for NetGen Functional SimulationOutput files for NetGen Functional Simulation Ngcbuildoptions toplevelnetlistfile outputngcfileSyntax for NetGen Timing Simulation Fpga Timing SimulationNetGen Timing Simulation Flow Output files for Fpga Timing Simulation Cpld Timing SimulationInput files for Cpld Timing Simulation Output files for Cpld Timing SimulationOptions for NetGen Simulation Flow Insertppbuffers Insert Path Pulse Buffers Mhf Multiple Hierarchical FilesModule Simulation of Active Module Ofmt Output Format Pcf PCF FileChange Speed Sim Generate Simulation NetlistTi Top Instance Name Tm Top Module NameTp Bring Out Global 3-State Net as Port Insertglbl Insert glbl.v ModuleNe No Name Escaping Pf Generate PIN FileSdfanno Include $sdfannotate Sdfpath Full Path to SDF FileVHDL-Specific Options for Functional and Timing Simulation NetGen Equivalence Checking Flow Xon Select Output Behavior for Timing ViolationsNetGen Equivalence Checking Flow Xon truefalseSyntax for NetGen Equivalence Checking Input files for NetGen Equivalence CheckingOutput files for NetGen Equivalence Checking Options for NetGen Equivalence Checking FlowEcn Equivalence Checking Module Verification of Active Module NetGen Static Timing Analysis Flow Ngm Design Correlation FileNetGen Static Timing Analysis Flow Input files for Static Timing Analysis Output files for Static Timing AnalysisSyntax for NetGen Static Timing Analysis Options for NetGen Static Timing Analysis Flow 336 Preserving and Writing Hierarchy Files Sta Generate Static Timing Analysis NetlistPreserving and Writing Hierarchy Files Modulename .sim Modulename .ecn Modulename .staDedicated Global Signals in Back-Annotation Simulation Testbench FileHierarchy Information File Global Signals in Verilog Netlist Global Signals in Vhdl NetlistDedicated Global Signals in Back-Annotation Simulation 340 Xflow Xflow OverviewXflow Syntax 1XFLOW Design FlowXflow Input Files Xflow Input FilesXflow Output Files Xflow Output Files 1XFLOW Output Files FPGAs and CPLDs2XFLOW Output Files FPGAs Assemble Module Assembly Xflow Flow TypesXflow Flow Types 3XFLOW Output Files CPLDsConfig Create a BIT File for FPGAs ConfigoptionfileEcn Create a File for Equivalence Checking 4Option Files for -assemble Flow Type DescriptionFit Fit a Cpld Fsim Create a File for Functional Simulation5Option Files for -ecn Flow Type Description 6Option Files for -fit Flow Type DescriptionImplement Implement an Fpga 7Option Files for -fsim Flow TypeXflow -p xc2v250fg256-5 -fsim genericverilog.opt testclk.v Implement optionfileInitial Initial Budgeting of Modular Design Xflow Flow Types 8Option Files for -implement Flow TypeInitial budget.opt Xflow -p xc2v250fg256-5 -initial budget.opt top.edfModule Active Module Implementation Moduleoptionfile -activemodulename9Option Files for -module Flow Type Mppr Multi-Pass Place and Route for FPGAs Sta Create a File for Static Timing Analysis10Option Files for -mppr Flow Type Description 11Option Files for -sta Flow Type DescriptionSynth Synthesis TypesSynthoptionfile Tsim Create a File for Timing Simulation Option Files for -synth Flow Types12Option Files for -synth Flow Type Description Testclk.prjFlow Files 13Option Files for -tsim Flow Type DescriptionFlow File Format FpgaFlag Enabled Disabled TriggersExports ReportsUser Command Blocks End Program programnameXflow Option Files Option File FormatXflow Options Active Active ModuleEd Copy Files to Export Directory Specify a Global VariableNorun Creates a Script File Only Change Output File NameOoutputfilename Xflow -implement balanced.opt -o newname testclk.edfPd PIMs Directory Rd Copy Report FilesPdpimdirectory RdreportdirectoryUsing Xflow Flow Types in Combination Running XflowWd Specify a Working Directory Running Smart FlowUsing the SCR, BAT, or TCL File Using the Xilxflowpath Environment VariableRunning Xflow 366 Data2MEM Data2MEM OverviewData2MEM Syntax Data2MEM Input and Output FilesBlock RAM Memory Map .bmm files Executable and Linkable Format .elf filesDebugging Information Format Dwarf .drf files Memory .mem filesBit .bit files Verilog .v files1Data2MEM Command Line Options Description Data2MEM OptionsVhdl .vhd files UCF .ucf filesData2MEM Options 1Data2MEM Command Line Options Pp filename Xilinx Development System Files Name Type Produced By DescriptionAppendix MOD Ascii Trace NKY TCL Ascii 378 EDIF2NGD, and NGDBuild EDIF2NGDEDIF2NGD Design Flow EDIF2NGD Syntax EDIF2NGD Input FilesEDIF2NGD Output Files Edif2ngd options ediffile ngofileAdd PADs to Top-Level Port Signals EDIF2NGD OptionsAul Allow Unmatched LOCs Libraries to Search Part NumberIgnore LOC Constraints LlibnameNGDBuild NGDBuild and the Netlist ReadersNGDBuild Netlist Launcher Netlister Bus MatchingBus Naming Conventions Busnameindex DI3Netlist Launcher Netlister Netlist Launcher Rules Files User Rules FileUser Rules and System Rules User Rules FormatDevelopment System Reference Guide 389 System Rules File Value Types in Key StatementsRules File Examples Example 1 Edfrule System RuleExample 2 User Rule Example 3 User RuleNGDBuild File Names and Locations Example 4 User RuleNGDBuild File Names and Locations 394 Glossary AbelAsic Bitstream BlockBonded Boundary scanBuft CAECLB CmosConfiguration ContentionCombinatorial logic CompilerCpld Daisy chainDangling bus Dangling netDRC DSPEDA EdifEprom FdsdFifo Fmap FpgaGlobal Set/Reset net Gate arrayGlobal buffers Global 3-state netHDL IbufIeee IFDJedec LSB MSB NCD NGMPAL PIM PLDProm RAMROM RPMRTL SDF standard delay format Set/resetSignal Startup symbolTCL Trace TsimTTL Wire VhdlVital Xtclsh422