Xilinx 8.2i manual Fn Control Flattening a Netlist, Module Verification of Active Module

Chapter 22: NetGen

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For additional information on equivalence checking and formal verification tools, please refer to the Synthesis and Simulation Design Guide.

–fn (Control Flattening a Netlist)

The –fn option produces a flattened netlist.

–intstyle (Integration Style)

–intstyle {ise xflow silent}

The –intstyle option reduces screen output based on the integration style you are running. When using the –intstyle option, one of three modes must be specified: ise, xflow, or silent. The mode sets the way information is displayed in the following ways:

–intstyle ise

This mode indicates the program is being run as part of an integrated design environment.

–intstyle xflow

This mode indicates the program is being run as part of an integrated batch flow.

–intstyle silent

This mode limits screen output to warning and error messages only.

Note: The -intstyle option is automatically invoked when running in an integrated environment, such as Project Navigator or XFLOW.

–mhf (Multiple Hierarchical Files)

The –mhf option is used to write multiple hierarchical files, one for every module that has the KEEP_HIERARCHY attribute.

–module (Verification of Active Module)

–module

The –module option creates a netlist file based on the active module, independent of the top-level design. NetGen constructs the netlist based only on the active module’s interface signals.

To use this option you must specify an NCD file that contains an expanded active module.

Note: This option is for use with the Modular Design flow.

–ne (No Name Escaping)

By default (without the –ne option), NetGen “escapes” illegal block or net names in your design by placing a leading backslash (\) before the name and appending a space at the end of the name. For example, the net name “p1$40/empty” becomes “\p1$40/empty” when name escaping is used. Illegal Verilog characters are reserved Verilog names, such as “input” and “output,” and any characters that do not conform to Verilog naming standards.

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