Timing Timing-Driven Packing and Placement

Chapter 7: MAP

–timing (Timing-Driven Packing and Placement)

Timing-driven packing and placement is recommended to improve design performance, timing, and packing for highly utilized designs. If the unrelated logic number (shown in the Design Summary section of the MAP report) is non-zero, then the –timing option is useful for packing more logic in the device. Timing-driven packing and placement is also recommended when there are local clocks present in the design.

Note: PAR issues a message to run timing-driven packing if it detects local clocks in the design. The –timing option is not supported on Virtex, Virtex-E, Spartan-II, and Spartan-IIE architectures.

The –timing option directs MAP to give priority to timing critical paths during packing, then places the design. Any user-generated timing constraints, contained in the UCF, drive the packing and placement operations. Use of the –timing option may result in longer runtime during the MAP process because designs are also placed; although, PAR runtime will be reduced since the placement phase is complete.

If Timing-driven packing and placement is selected in the absence of user timing constraints, the tools will automatically generate and dynamically adjust timing constraints for all internal clocks. This feature is referred to as “Performance Evaluation” mode. This mode allows the clock performance for all clocks in the design to be evaluated in one pass. The performance achieved by this mode is not necessarily the best possible performance each clock can achieve, instead it is a balance of performance between all clocks in the design.

The –ol option is used in conjunction with the –timing option to set the overall effort level that MAP uses to pack, and then place the design. See “–ol (Overall Effort Level)” for more information.

Note: The following options are specific to timing-driven packing and placement (–timing): –ol, –register_duplication, –t, and –xe. See individual option descriptions in this section for details.

–tx (Transform Buses)

–tx {on off aggressive limit}

The –tx option specifies what type of bus transformation MAP performs. The four permitted settings are on, off, aggressive, and limit. The following example shows how the settings are used. In this example, the design has the following characteristics and is mapped to a Virtex device:

•Bus A has 4 BUFTs

•Bus B has 20 BUFTs

•Bus C has 30 BUFTs

MAP processes the design in one of the following ways, based on the setting used for the –tx option:

•The on setting performs partial transformation for a long chain that exceeds the device limit.

♦Bus A is transformed to LUTs (number of BUFTs is >1, ≤4)

♦Bus B is transformed to CY chain (number of BUFTs is >4, ≤48)

♦Bus C is partially transformed. (25 BUFTs + 1 dummy BUFT due to the maximum width of the XCV50 device + CY chain implementing the other 5 BUFTs)

•The off setting turns bus transformation off. This is the default setting.

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Development System Reference Guide

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Xilinx 8.2i manual Timing Timing-Driven Packing and Placement, Tx Transform Buses

Models: 8.2i