Manuals / Xilinx / Marine Equipment / Life Jacket

Xilinx 8.2i manual TAEngine Overview

Models: 8.2i

1 422

Download 422 pages 26.35 Kb

Page 309

Image 309

Chapter 20

TAEngine

TAEngine is compatible with the following families:

•CoolRunner™ XPLA3, CoolRunner™-II

•XC9500™, XC9500XL™, XC9500XV™

This chapter describes the Timing Analysis Engine (TAEngine) program. TAEngine is a command line executable that performs static timing analysis on implemented Xilinx CPLD designs. This chapter includes the following sections:

•“TAEngine Overview”

•“TAEngine Syntax”

•“TAEngine Input Files”

•“TAEngine Output Files”

•“TAEngine Options”

TAEngine Overview

TAEngine takes an implemented CPLD design file (VM6) from CPLDfit and performs a static timing analysis of the design’s timing components. The results of the static timing analysis are written to a TAEngine report file (TIM) in summary or detail format.

The default output for TAEngine is a TIM report in summary format, which lists all timing paths and their delays. A detail formatted TIM report, specified with the “–detail (Detail Report)” option, lists all timing paths as well as a summary of all individual timing components that comprise each path. Both the summary and detail formatted TIM reports show the performance of all timing constraints contained in the design.

Development System Reference Guide

www.xilinx.com

309

Page 309

Image 309

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Contents

Development System Reference Guide Development System Reference Guide About This Guide Guide ContentsPreface About This Guide Additional Resources ConventionsTypographical Preface About This Guide Convention Meaning or Use Example Online DocumentAllow block blockname Loc1 loc2 ... locnTable of Contents Tcl PARTGen Logical Design Rule Check NGDBuildMAP PAR Physical Design Rule CheckDevelopment System Reference Guide PIN2UCF XPowerTrace Output Files TraceBitGen SpeedprintBSDLAnno IBISWriter PROMGenCPLDfit TsimTAEngine NetGen Hprep6Development System Reference Guide Xflow EDIF2NGD, and NGDBuild Data2MEMCommand Line Program Overview 1Command Line Programs in the Design Flow Design Flow StepIntroduction Command Line Options Command Line SyntaxExecute Commands File IntroductionCommand Line Options Symbol DescriptionHelp Intstyle Integration Style Introduction Symbol DescriptionProgramname -harchitecturename Programname -h filenamePart Number 2Part Number Examples SpecificationIntroduction 2Part Number Examples Specification Invoking Command Line ProgramsDesign Flow Overview Design FlowXilinx Design Flow Design Flow2Xilinx Software Design Flow FPGAs Design Flow Overview3Xilinx Software Design Flow CPLDs Design Entry and Synthesis Hierarchical DesignDesign Entry and Synthesis Schematic Entry Overview Library ElementsCore Generator Tool FPGAs Only Functional Simulation HDL Entry and SynthesisConstraints Mapping Constraints FPGAs OnlyTiming Specifications Block PlacementDesign Implementation Netlist Translation Programs5Design Implementation Flow FPGAs Design Implementation6Design Implementation Flow CPLDs Mapping FPGAs Only Placing and Routing FPGAs OnlyBitstream Generation FPGAs Only 1Verification Tools Verification Type Design Verification7Three Verification Methods of the Design Flow FPGAs Design VerificationBack-Annotation Simulation9Back-Annotation Flow for FPGAs NetGen Schematic-Based SimulationTiming Simulation HDL-Based Simulation2Five Simulation Points in HDL Design Flow UniSim SimPrim 11Simulation Points for HDL DesignsStatic Timing Analysis FPGAs Only Design Rule Checker FPGAs Only In-Circuit VerificationXilinx Design Download Cables ProbeFpga Design Tips 3Global Clock Resources Fpga Family Number Destination PinsDesign Size and Performance Global Clock Distribution12 Gated Clock Data Feedback and Clock EnableCounters 13Synchronous Design Using Data FeedbackOther Synchronous Design Considerations Q0. . . .Q7 Q8. . . .Q15Q0. . . .Q7Q8. . . .Q15 Tcl Overview TclXilinx Tcl Shell Accessing HelpTcl Fundamentals Tcl FundamentalsXilinx Tcl Commands 1Xilinx Tcl Commands for General Usage SubcommandsXilinx Namespace Project create and manage projects Tcl Commands for General Usage 2Xilinx Tcl Commands for Advanced Scripting SubcommandsPartition support design preservation Delete delete a partition Tcl Commands for General UsageGet get partition properties Partition delete /stopwatch/Instdcm1New create a new partition Partition get /stopwatch/Instdcm1 preservePartition new /stopwatch/Instdcm1 Properties list available partition properties Rerun force partition synthesis and implementationPartition properties Set set partition preserve property Process run and manage project processes Run run process task4Process Tasks Clean remove system-generated project files Project cleanProject create and manage projects Get get project properties Close close the ISE projectGetprocesses get project processes Project closeOpen open an ISE project New create a new ISE projectProject getprocesses -instance Instdcm1 Project new watchver.iseProperties list project properties Set set project properties, values, and optionsProject properties -process all Set family set device family Set device set deviceProject set Map Effort Level high Project set device xc2vp2Set speed set device speed Set package set device packageProject set family Virtex2p Project set package fg256Set top set the top-level module/entity Timinganalysis generate timing analysis reportsDelete delete timing analysis Project set speedDisablecpt disable components for path tracing control Disableconstraints disable timing constraintsTiminganalysis enableconstraints Enablecpt enable components for path tracing controlStopwatchtiming TSclk=PERIOD TIMEGROUP\sclk\ Ns High 50.00000%Timinganalysis enablecpt stopwatchtiming Get get analysis propertyRegsrclk ureg1 ureg2 ureg3 Ascii New new timing analysis Timinganalysis reset stopwatchtiming Reset reset path filters and constraintsRun run analysis Saveas save analysis reportSetconstraint set constraint for custom analysis Set set analysis propertiesTiminganalysis set stopwatchtiming AnalysisspeedSetendpoints set source and destination endpoints Timinganalysis setconstraint stopwatchtimingPeriod 13 sclk Setfilter set filter for analysis Setquery set up net or timegroup reportTiminganalysis setfilter stopwatchtiming nets Exclude uregnet1 uregnet2 uregnet3Xfile manage project files Showsettings generate settings reportAdd add file to project ExampleRemove remove file from project Get get project file propertiesXfile add *.vhd /mysource/mysubdir timing.ucf Xfile get timestamp stopwatch.vhdCollection create and manage a collection Tcl Commands for Advanced ScriptingAppendto add objects to a collection Xfile remove stopwatch.vhdCopy copy a collection Tcl Commands for Advanced ScriptingSet colVar1 search * -type instance Set colVar2 $colVar1Set colVar2 collection copy $colVar1 Equal compare two collectionsSet colVar2 search /top/T* -type instance Collection equal $colVar1 $colVar2Get get collection property Foreach iterate over elements in a collectionProperties list available collection properties Index extract a collection objectSet item collection index $colVar Object name $itemRemovefrom remove objects from a collection Set set the property for all collectionsCollection properties Sizeof show the number of objects in a collection Object get object informationCollection set displaytype true Collection sizeof $colVarName name of the object Get get object propertiesCollection foreach obj $colVar set objProps Object properties $obj foreach prop $objPropsProperties list object properties Object name collection index $colVarSet colVar search * -type partition Search search and return matching objects Type type of objectObject type collection index $colVar Search /stopwatch -type instance Project Properties and Options6Project Properties Property Name Description Option Name Synthesis ToolProject Properties and Options NGDBuild Options Option Name Implementation Tool Option Name Implementation Tool Tcl 10 PAR Options Example Tcl Scripts Sample Tcl Script for General UsageExample Tcl Scripts Tcl Sample Tcl Script for Advanced Scripting 100 PARTGen Overview PARTGenPARTGen Syntax Partgen optionsPARTGen Output Files PARTGen Input FilesPARTGen Options Arch Print Information for Specified ArchitecturePARTGen Options Print a List of Devices, Packages, and Speeds PARTGen Options 2s400e Nopkgfile No Package File Creates Package file and Partlist FilesPname Xcv400 Device V400bg432 PartCreates Package and Partlist Files Partlist FileDevice Attributes HeaderPartlist File Part architecture family partname diename packagefilenameSelect RAM PKG File PKG FileDone Logical DRC Overview Logical Design Rule CheckBlock Check Logical DRC ChecksNet Check Pad CheckClock Buffer Check Name CheckLogical DRC Checks Primitive Pin Check 1Checked Primitive Pins NGD Primitive Pins CheckedNGDBuild Overview NGDBuild1NGDBuild Design Flow Converting a Netlist to an NGD FileNGDBuild Input Files NGDBuild SyntaxNGDBuild Syntax Ngdbuild options designname ngdfile.ngd120 NGDBuild Output Files Add PADs to Top-Level Port SignalsNGDBuild Intermediate Files NGDBuild OptionsBm Specify BMM Files Aul Allow Unmatched LOCsDd Destination Directory Ignore UCF FileLibraries to Search InsertkeephierarchyNGDBuild Options SynopsysModular initial Initial Budgeting of Modular Design Modular assemble Module AssemblyModular assemble -pimpath pimdirectorypath Usepimmodulename1 -usepimmodulename2Nt Netlist Translation Type Modular module Active Module ImplementationModular module -active modulename Pimcreate pimdirectory -ncd designnamerouted.ncdIgnore LOC Constraints Sd Search Specified DirectoryAllow Unexpanded Blocks Ur Read User Rules File Uc User Constraints FileVerbose Report All Messages Uc ucffile.ucf128 MAP Overview MAPMap options infile.ngd pcffile.pcf MAP SyntaxMAP Input Files MAP Output FilesMAP Input Files 1Map Options and Architectures MAP OptionsPack CLBs Bp Map Slice LogicMAP Options 1Map Options and Architectures CpackfactorDetail Write Out Detailed MAP Report Cm Cover ModeEquivalentregisterremoval Remove Redundant Registers Cm area speed balancedGm incremental Guide Mode incremental Gm Guide ModeGf Guide NCD File Globalopt Global OptimizationIr Do Not Use RLOCs to Generate RPMs Ignorekeephierarchy Ignore Keephierarchy PropertiesIse ISE Project File Map to Input FunctionsOutput File Name No logic replicationOlstdmedhigh Ol Overall Effort LevelNo Register Ordering Pr Pack Registers in I/ORegisterduplication Duplicate Registers Retiming Register Retiming During Global OptimizationTiming Timing-Driven Packing and Placement Tx Transform BusesTx on off aggressive limit Do Not Remove Unused Logic MAP ProcessXe Extra Effort Level MAP ProcessRegister Ordering Data01 Addr02 Atod03 Dtoa04 Register Ordering3Guided Mapping Guided MappingSimulating Map Results Simulating Map Results4Logical Circuit Representation MAP Report MRP File MAP Report MRP File148 Development System Reference Guide 149 Type Block GND Xstgnd IOB 152 Halting MAP Halting MAP154 DRC Overview Physical Design Rule CheckDRC Input File DRC SyntaxDRC Output File DRC OptionsDRC Checks Report Incomplete ProgrammingDRC Checks DRC Errors and Warnings Place and Route Overview PARPAR Flow Placing PAR ProcessRouting Timing-driven PARCommand Line Examples Par input.ncd output.ncdPar -k previous.ncd reentrant.ncd pref.pcf Guided PAR Guided PARPCI Cores PAR Input Files PAR SyntaxPAR Output Files PAR SyntaxGeneral Options Function Range Default 1Effort Level Options Function Range DefaultPAR Options Ol value for the routerPAR Options 2General Options Function Range Default Guide Options Function Range DefaultExistingfile Execute Commands File Detailed Listing of OptionsGf Guide NCD File Intstyle Integration Style Gm Guide ModeRe-Entrant Routing PAR OptionsNumber of PAR Iterations Multi-Tasking ModeNopad No Pad Ol Overall Effort LevelPower Power Aware PAR No PlacementPl Placer Effort Level No RoutingStarting Placer Cost Table Number of Results to SaveUb Use Bonded I/Os Overwrite Existing FilesPAR Reports Performance Evaluation ModeXe Extra Effort Level PAR ReportsPlace and Route Report File Development System Reference Guide 175 Ing score in parenthesis Development System Reference Guide 177 Multi Pass Place and Route Mppr Placer effort levelrouter effort levelcost table numberPar -n 3 -pl high -rl std address.ncd output.dir Importing the PAD File Information Select I/O Utilization and Usage SummaryGuide Reporting Multi Pass Place and Route MpprXplorer Best Performance ModeTiming Closure Mode Xplorer SyntaxXplorer Xplorer Output Files Xplorer Input FilesXplorer Options 5Xplorer Options FunctionXplorer 5Xplorer Options Function Xplorer Report184 ReportGen Syntax ReportGenReportGen Input Files ReportGen Output FilesOption Usage Function ReportGen OptionsIsexflowsilent Padfmt padcsvtxtTurns Engine Overview Turns Engine PAR Multi-Tasking OptionTurns Engine PAR Multi-Tasking Option Par -m nodefilename -ol high -n 10 mydesign.ncd output.dirTurns Engine Input Files Turns Engine SyntaxTurns Engine Output Files LimitationsSystem Requirements Turns Engine Environment Variables Rsh machinename DebuggingScreen Output Node Status JOB Time Halting PAR Halting PAR 196 XPower Overview XPowerFiles Used by XPower XPower SyntaxFpga Designs Cpld DesignsUsing XPower Using XPowerVCD Data Entry Other Methods of Data Entry Rename Power ReportLimit Ls List Supported DevicesSpecify VCD file Specify Settings XML Input FileTb Turn On Time Based Reporting Wx Write XML FileCommand Line Examples Power ReportsStandard Reports Power Reports Detailed ReportsAdvanced Reports 204 PIN2UCF Overview PIN2UCFPIN2UCF Flow PIN2UCF Input Files PIN2UCF SyntaxPIN2UCF Output Files PIN2UCF SyntaxPIN2UCF Scenarios PIN2UCF OptionsWrite to a Report File Outfile.ucfExisting Pinlock section. 210 Trace Overview TraceTrace Input Files Trace SyntaxTrce options design.ncd constraint.pcf Trce -runmacro.xtm design.ncd constraint.pcfTrace Output Files Input files to TraceTrace Output Files Trace Options Generate an Error ReportAdvanced Analysis Fastpaths Report Fastest PathsLimit Timing Report Nodatasheet No Data SheetOutput Timing Report File Name Trace OptionsChange Speed Run Run Timing Analyzer MacroSkew Analyze Clock Skew for All Clocks SkewReport Uncovered Paths Stamp Generates Stamp timing model filesStampstampfile design.ncd UlimitGenerate a Verbose Report Trace Command Line ExamplesXml XML Output File Name VlimitTrace Reports Trace ReportsPath Delay Constraints Net Delay ConstraintsTiming Verification with Trace Net Skew Constraints1Path Delay Constraint Terminology Definition Clock Skew and Setup Checking2Clock Skew Example 2Clock Skew and Setup Checking Terminology Terms Definition3Clock Passing Through Multiple Buffers Reporting with Trace 5Error reporting for failed timing constraints Data Sheet Report Development System Reference Guide 227 BSLOT0 D0S Report Legend Guaranteed Setup and Hold ReportingHold Times Setup TimesTrce -o summary.twr ramb16s1.ncd Summary Report Without a Physical Constraints File SpecifiedTrce -o summary1.twr ramb16s1.ncd clkperiod.pcf Development System Reference Guide 233 Trce -e 3 ramb16s1.ncd clkperiod.pcf -o errorreport.twr Development System Reference Guide 235 236 Development System Reference Guide 237 BUFGMUX.I0 Offset Constraints Offset ConstraintsOffset in Constraint Examples Offset in HeaderOffset in Path Details Offset in Detailed Path Data Offset in Detail Path Clock Path Offset In with Phase Shifted ClockDevelopment System Reference Guide 243 Offset OUT Header Offset OUT Constraint ExamplesOffset OUT Detail Clock Path Offset OUT Path DetailsOffset OUT Detail Path Data Period Constraints Examples Period ConstraintsPeriod Header Period ConstraintsPeriod Path Period Path Details Period Constraint with Phase Period Path with Phase Minimum Period Statistics Halting TraceSpeedprint Overview SpeedprintSpeedprint Syntax Specify TemperatureSpeedprint Options Min Display Minimum Speed DataSpeedprint Example Commands Speedprint Example CommandsCommand Description Speedprint Example ReportsLvttl Fast BitGen Overview BitGenBitGen Syntax Option Output FileLoutfilename.ll Moutfilename.msk Boutfilename.rbt BitGen Input Files BitGen Output FilesBitGen Input Files Create Rawbits File BitGen OptionsSet Configuration Bd Update Block RamsBitgen -goptionsetting design.ncd design.bit design.pcf Do Not Run DRCActivateGCLK ActiveReconfigBinary CclkPinCompress ConfigRateDCIUpdateMode DCMShutdownDebugBitstream DONEcycle DisableBandgapDonePin DonePipeEncrypt DriveDoneGclkdel0, Gclkdel1, Gclkdel2, Gclkdel3 GSRcycleGTScycle GWEcycleHswapenPin Key0, Key1, Key2, Key3, Key4, Key5Keyseq0, Keyseq1, Keyseq2, Keyseq3, Keyseq4, Keyseq5 KeyFileLCKcycle M0PinM2Pin M1PinMatchcycle PartialGCLKPartialLeft PartialMask0, PartialMask1, PartialMask2PartialRight PersistProgPin PowerdownPinReadBack SecurityStartCBC SEURepairStartKey StartupClkTdiPin TckPinTdoPin TmsPinNo BIT File UnusedPinUserID Generate a Mask File Create a Logic Allocation FileCreate a Partial Bit File Overwrite Existing Output File276 BSDLAnno Overview BSDLAnnoBSDLAnno Input Files BSDLAnno SyntaxBSDLAnno Output Files BSDLAnno OptionsEntity Declaration BSDLAnno File CompositionGeneric Parameter BSDLAnno File CompositionPackage Pin-Mapping Logical Port DescriptionUSE Statement Scan Port IdentificationTAP Description Boundary Register Description Bsdl File Modifications for Single-Ended PinsExplanation Modifications to the Designwarning Section Boundary Scan Behavior in Xilinx DevicesHeader Comments BSDLAnno BSDLAnno version numberPROMGen Overview PROMGenPROMGen Input Files PROMGen SyntaxPROMGen Output Files Promgen optionsPROMGen Options Prom Format Add BIT FIlesLoad Prom File File1.bit file2.bitTemplate File Prom SizeLoad Upward Ver VersionBit Swapping in Prom Files Enable CompressionPROMGen Examples PROMGen Examples292 IBISWriter Overview IBISWriterIbiswriter options infile outfile.ibs IBISWriter SyntaxIBISWriter Output Files IBISWriter Input FilesIBISWriter Options Set Reference VoltageArchitecture Option Value Description Ml Multilingual SupportIBISWriter Options Pin Generate Package Parasitics298 CPLDfit Overview CPLDfitCPLDfit Syntax CPLDfit Input FilesCPLDfit Output Files CPLDfit Options Iostd Specify I/O Standard Inputs Number of Inputs to Use During OptimizationKeepio Prevent Optimization of Unused Inputs Loc Keep Specified Location ConstraintsNogclkopt Disable Global Clock Optimization Nofbnand Disable Use of Foldback NandsNogsropt Disable Global Set/Reset Optimization Nogtsopt Disable Global Output-Enable OptimizationOptimize Optimize Logic for Density or Speed Power Set Power ModeSpecify Xilinx Part Pinfbk Use Pin FeedbackUnused Set Termination Mode of Unused I/Os Terminate Set to Termination ModeSlew Set Slew Rate Wysiwyg Do Not Perform Optimization306 Tsim Syntax TsimTsim Input Files TAEngine Overview TAEngine1TAEngine Design Flow TAEngine SyntaxDetail Detail Report TAEngine OptionsIopath Trace Paths Specify Output Filename312 1Hprep6 Design Flow Hprep6Hprep6 Syntax Hprep6 OptionsAutosig Automatically Generate Signature Specify Signature Value for Readback Nopullup Disable PullupsProduce ISC File Tmv Specify Test Vector File316 NetGen Overview NetGen1NetGen Output File Types Input Design File NetGenNetGen Functional Simulation Flow NetGen Simulation FlowNetGen Supported Flows NetGen Simulation FlowSyntax for NetGen Functional Simulation NetGen Timing Simulation FlowOutput files for NetGen Functional Simulation Ngcbuildoptions toplevelnetlistfile outputngcfileSyntax for NetGen Timing Simulation Fpga Timing SimulationNetGen Timing Simulation Flow Cpld Timing Simulation Output files for Fpga Timing SimulationInput files for Cpld Timing Simulation Output files for Cpld Timing SimulationOptions for NetGen Simulation Flow Insertppbuffers Insert Path Pulse Buffers Mhf Multiple Hierarchical FilesModule Simulation of Active Module Pcf PCF File Ofmt Output FormatChange Speed Sim Generate Simulation NetlistTm Top Module Name Ti Top Instance NameTp Bring Out Global 3-State Net as Port Insertglbl Insert glbl.v ModulePf Generate PIN File Ne No Name EscapingSdfanno Include $sdfannotate Sdfpath Full Path to SDF FileVHDL-Specific Options for Functional and Timing Simulation Xon Select Output Behavior for Timing Violations NetGen Equivalence Checking FlowNetGen Equivalence Checking Flow Xon truefalseInput files for NetGen Equivalence Checking Syntax for NetGen Equivalence CheckingOutput files for NetGen Equivalence Checking Options for NetGen Equivalence Checking FlowEcn Equivalence Checking Module Verification of Active Module NetGen Static Timing Analysis Flow Ngm Design Correlation FileNetGen Static Timing Analysis Flow Input files for Static Timing Analysis Output files for Static Timing AnalysisSyntax for NetGen Static Timing Analysis Options for NetGen Static Timing Analysis Flow 336 Sta Generate Static Timing Analysis Netlist Preserving and Writing Hierarchy FilesPreserving and Writing Hierarchy Files Modulename .sim Modulename .ecn Modulename .staDedicated Global Signals in Back-Annotation Simulation Testbench FileHierarchy Information File Global Signals in Verilog Netlist Global Signals in Vhdl NetlistDedicated Global Signals in Back-Annotation Simulation 340 Xflow Overview Xflow1XFLOW Design Flow Xflow SyntaxXflow Input Files Xflow Input FilesXflow Output Files 1XFLOW Output Files FPGAs and CPLDs Xflow Output Files2XFLOW Output Files FPGAs Xflow Flow Types Assemble Module AssemblyXflow Flow Types 3XFLOW Output Files CPLDsConfigoptionfile Config Create a BIT File for FPGAsEcn Create a File for Equivalence Checking 4Option Files for -assemble Flow Type DescriptionFsim Create a File for Functional Simulation Fit Fit a Cpld5Option Files for -ecn Flow Type Description 6Option Files for -fit Flow Type Description7Option Files for -fsim Flow Type Implement Implement an FpgaXflow -p xc2v250fg256-5 -fsim genericverilog.opt testclk.v Implement optionfileXflow Flow Types 8Option Files for -implement Flow Type Initial Initial Budgeting of Modular DesignInitial budget.opt Xflow -p xc2v250fg256-5 -initial budget.opt top.edfModule Active Module Implementation Moduleoptionfile -activemodulename9Option Files for -module Flow Type Sta Create a File for Static Timing Analysis Mppr Multi-Pass Place and Route for FPGAs10Option Files for -mppr Flow Type Description 11Option Files for -sta Flow Type DescriptionSynth Synthesis TypesSynthoptionfile Option Files for -synth Flow Types Tsim Create a File for Timing Simulation12Option Files for -synth Flow Type Description Testclk.prj13Option Files for -tsim Flow Type Description Flow FilesFpga Flow File FormatTriggers Flag Enabled DisabledExports ReportsEnd Program programname User Command BlocksOption File Format Xflow Option FilesActive Active Module Xflow OptionsEd Copy Files to Export Directory Specify a Global VariableChange Output File Name Norun Creates a Script File OnlyOoutputfilename Xflow -implement balanced.opt -o newname testclk.edfRd Copy Report Files Pd PIMs DirectoryPdpimdirectory RdreportdirectoryRunning Xflow Using Xflow Flow Types in CombinationWd Specify a Working Directory Running Smart FlowUsing the SCR, BAT, or TCL File Using the Xilxflowpath Environment VariableRunning Xflow 366 Data2MEM Overview Data2MEMData2MEM Input and Output Files Data2MEM SyntaxBlock RAM Memory Map .bmm files Executable and Linkable Format .elf filesMemory .mem files Debugging Information Format Dwarf .drf filesBit .bit files Verilog .v filesData2MEM Options 1Data2MEM Command Line Options DescriptionVhdl .vhd files UCF .ucf filesData2MEM Options 1Data2MEM Command Line Options Pp filename Name Type Produced By Description Xilinx Development System FilesAppendix MOD Ascii Trace NKY TCL Ascii 378 EDIF2NGD EDIF2NGD, and NGDBuildEDIF2NGD Design Flow EDIF2NGD Input Files EDIF2NGD SyntaxEDIF2NGD Output Files Edif2ngd options ediffile ngofileAdd PADs to Top-Level Port Signals EDIF2NGD OptionsAul Allow Unmatched LOCs Part Number Libraries to SearchIgnore LOC Constraints LlibnameNGDBuild and the Netlist Readers NGDBuildNGDBuild Bus Matching Netlist Launcher NetlisterBus Naming Conventions Busnameindex DI3Netlist Launcher Netlister User Rules File Netlist Launcher Rules FilesUser Rules and System Rules User Rules FormatDevelopment System Reference Guide 389 Value Types in Key Statements System Rules FileExample 1 Edfrule System Rule Rules File ExamplesExample 3 User Rule Example 2 User RuleNGDBuild File Names and Locations Example 4 User RuleNGDBuild File Names and Locations 394 Abel GlossaryAsic Block BitstreamBonded Boundary scanCAE BuftCmos CLBContention ConfigurationCombinatorial logic CompilerDaisy chain CpldDangling bus Dangling netDSP DRCEdif EDAEprom FdsdFifo Fpga FmapGate array Global Set/Reset netGlobal buffers Global 3-state netIbuf HDLIFD IeeeJedec LSB MSB NGM NCDPAL PLD PIMRAM PromROM RPMRTL Set/reset SDF standard delay formatSignal Startup symbolTCL Tsim TraceTTL Vhdl WireVital Xtclsh422