Xilinx 8.2i Ti Top Instance Name, Tm Top Module Name, Tp Bring Out Global 3-State Net as Port

Chapter 22: NetGen

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–ti (Top Instance Name)

–titop_instance_name

The –ti option specifies a user instance name for the design under test in the testbench file created with the –tb option.

–tm (Top Module Name)

–tmtop_module_name

By default (without the –tm option), the output files inherit the top module name from the input NCD file. The –tm option changes the name of the top-level module name appearing in the NetGen output files.

–tp (Bring Out Global 3-State Net as Port)

–tpport_name

The –tp option causes NetGen to bring out the global 3-state signal (which forces all FPGA outputs to the high-impedance state) as a port on the top-level design module or output file. Specifying the port name allows you to match the port name you used in the front-end.

This option is only used if the global 3-state net is not driven. For example, if you include a STARTUP_VIRTEX component in an Virtex-E design, you should not have to enter a –tp option, because the STARTUP_VIRTEX component drives the global 3-state net.

Note: Do not use the name of any wire or port that already exists in the design, because this causes NetGen to issue an error. This option is ignored in UNISIM-based flows, which use an NGC file as input.

–w (Overwrite Existing Files)

The –w option causes NetGen to overwrite the .vhd or .v file if it exists. By default, NetGen does not overwrite the netlist file.

Note: All other output files are automatically overwritten.

Verilog-Specific Options for Functional and Timing Simulation

This section describes the Verilog-specific command line options for timing simulation.

–insert_glbl (Insert glbl.v Module)

–insert_glbl truefalse

The –insert_glbl option specifies that the glbl.v module is included in the output Verilog simulation netlist. The default value of this option is true. The –insert_glbl option when set to false, specifies that the output Verilog netlist will not contain the glbl.v module. For more information on glbl.v, see the Synthesis and Simulation Design Guide.

Note: If the –mhf (multiple hierarchical files) option is used, –insert_glbl cannot be set to true.

–ism (Include SimPrim Modules in Verilog File)

The –ism option includes SimPrim modules from the SimPrim library in the output Verilog (.v) file. This option allows you to bypass specifying the library path during simulation. However, using this switch increases the size of your netlist file and increases your compile time.

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