Chapter 4: PARTGen

R

•External Clock IOB pins:

♦For Virtex, Virtex-E, Spartan-II, and Spartan-3E

GCLKBUF0=PAD#, GCLKBUF1=PAD#, GCLKBUF2=PAD#, GCLKBUF3=PAD#

♦For Virtex-II, Virtex-II Pro, and Virtex-4:

BUFGMUX0P=PAD#, BUFGMUX1P=PAD#,

BUFGMUX2P=PAD#, BUFGMUX3P=PAD#, BUFGMUX4P=PAD#, BUFGMUX5P=PAD#,

BUFGMUX6P=PAD#, BUFGMUX7P=PAD#

•Block RAM:

NUM_BLK_RAMS=#

BLK_RAM_COLS=# BLK_RAM_COL0=# BLK_RAMCOL1=# BLK_RAM_COL2=# BLK_RAM_COL_3=#

BLK_RAM_SIZE=4096x1 BLK_RAM_SIZE=2048x2 BLK_RAM_SIZE=512x8 BLK_RAM_SIZE=256x16

Block RAM locations are given with reference to CLB columns. In the following example, Block RAM 5 is positioned in CLB column 32.

NUM_BLK_RAMS=10 BLK_RAM_COL_5=32 BLK_RAM_SIZE=4096X1

•Select RAM:

NUM_SEL_RAMS=# SEL_RAM_SIZE=#X#

•Select Dual Port RAM:

SEL_DP_RAM={TRUEFALSE}

This field indicates whether the select RAM can be used as a dual port ram. The assumption is that the number of addressable elements is reduced by half, that is, the size of the select RAM in Dual Port Mode is half that indicated by SEL_RAM_SIZE.

•Speed grade information: SPEEDGRADE=#

•Typical delay across a LUT for each speed grade: LUTDELAY=#

•Typical IOB input delay: IOB_IN_DELAY=#

•Typical IOB output delay: IOB_OUT_DELAY=#

•Maximum LUT constructed in a slice:

MAX_LUT_PER_SLICE=#

(From all the LUTs in the slice)

•Max LUT constructed in a CLB: MAX_LUT_PER_CLB=#

This field describes how wide a LUT can be constructed in the CLB from the available LUTs in the slice.

110

www.xilinx.com

Development System Reference Guide

Page 109 Page 111
Page 110
Image 110
Xilinx 8.2i manual Select RAM
Page 109 Page 111

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.
Top Page Image Contents