Xilinx 8.2i manual Xflow Output Files, 1XFLOW Output Files FPGAs and CPLDs

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XFLOW Output Files

The following table lists files that can be generated for both FPGA and CPLD designs.

Table 23-1:XFLOW Output Files (FPGAs and CPLDs)

File Name	Description	To Generate this File...
design_name.bld	This report file contains information about the	Flow file must include “ngdbuild” (Use
	NGDBuild run, in which the input netlist is	the –implement or –fit flow type)
	translated to an NGD file.
time_sim.sdf	This Standard Delay Format file contains the	Flow file must include “netgen” (Use the
func_sim.sdf	timing data for a design.	–tsim or –fsim flow type)
		Input must be an NGA file, which
		includes timing information
time_sim.tv	This is an optional Verilog test fixture file.	Flow file must include “netgen” (Use the
func_sim.tv		–tsim or –fsim flow type)
time_sim.tvhd	This is an optional VHDL testbench file.	Flow file must include “netgen” (Use the
func_sim.tvhd		–tsim or –fsim flow type)
time_sim.v	This Verilog netlist is a	Flow file must include “netgen” (Use the
func_sim.v	simulation netlist expressed in terms of Xilinx	–tsim or –fsim flow type)
	simulation primitives. It differs from the Verilog
	input netlist and should only be used for
	simulation, not implementation.
time_sim.vhd	This VHDL netlist is a simulation netlist	Flow file must include “netgen” (Use the
func_sim.vhd	expressed in terms of Xilinx simulation	–tsim or –fsim flow type)
	primitives. It differs from the VHDL input netlist
	and should only be used for simulation, not
	implementation.

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