R

PERIOD Constraints

PERIOD Path with Phase

This is similar to the PERIOD constraint (without PHASE). The difference for this path is the source and destination clock. The destination clock defines which PERIOD constraint the path uses. Because the destination clock is the rclk_90, this path is in the TS_rclk90_dcm PERIOD and not the TS_rclk PERIOD constraint.

Notice the Requirement is now 2.5 ns and not 10 ns. This is the amount of time between the source clock (rising at 0ns) and the destination clock (rising at 2.5 ns).

Because the slack is negative, this path fails the constraint. In the Hierarchical Report

Browser, this failing path is displayed in red.

Example:

----------------------------------------------------------------------

Slack:

 

-2.871ns (requirement - (data path - clock skew

+ uncertainty))

 

 

Source:

 

rd_addr[1] (FF)

Destination:

 

ffl_reg (FF)

Requirement:

 

2.500ns

Data Path Delay:

 

5.224ns (Levels of Logic = 2)

Clock Skew:

-0.147ns

Source Clock:

 

rclk rising at 0.000ns

Destination Clock:

rclk_90 rising at 2.500ns

Clock Uncertainty:

0.000ns

Data Path: rd_addr[1] to ffl_reg

 

 

Location

Delay type

Delay(ns) Logical Resource(s)

-------------------------------------------------

-------------------

SLICE_X4Y19.XQ

Tcko

0.568

rd_addr[1]

SLICE_X2Y9.F3

net (fanout=40)

1.700

rd_addr[1]

SLICE_X2Y9.X

Tilo

0.439

 

full_st_i_0.G_4.G_4.G_3_10

 

 

SLICE_X2Y11.F2

net (fanout=1)

0.459

G_3_10

SLICE_X2Y11.X

Tilo

0.439

 

full_st_i_0.G_4.G_4.G_4

 

 

K4.O1

net (fanout=3)

1.230

G_4

K4.OTCLK1

Tioock

0.389

ffl_reg

Development System Reference Guide

www.xilinx.com

251

Page 250 Page 252
Page 251
Image 251
Xilinx 8.2i manual Period Path with Phase
Page 250 Page 252

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

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