Xilinx 8.2i manual Offset Constraints

	R					OFFSET Constraints
	Data Sheet report:
-----------------
	All values displayed in nanoseconds (ns)
	Setup/Hold to clock clk
	---------------	+------------		+	------------	+
			Setup to		Hold to
	Source Pad	clk (edge) clk (edge)
	---------------	+------------		+	------------	+
	ad0		-0.013(R)		0.325(R)
	ad1		-0.013(R)		0.325(R)
	ad10		-0.013(R)		0.325(R)
	ad11		-0.013(R)		0.325(R)
.
.
.
	---------------	+------------		+	------------	+
	Clock clk to Pad
	---------------	+------------		+
		clk (edge)
	Destination Pad		to PAD
	---------------	+------------		+
	d0		9.563(R)
	---------------	+------------		+
	Timing summary:
---------------
	Timing errors:	1	Score: 587

Constraints cover 19 paths, 0 nets, and 21 connections (100.0% coverage)

Design statistics:

Maximum path delay from/to any node: 8.587ns

Maximum input arrival time after clock: 9.224ns

Analysis completed Mon Jun 03 17:57:24 2005

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OFFSET Constraints

OFFSET constraints define Input and Output timing constraints with respect to an initial time of 0ns.

The associated PERIOD constraint defines the initial clock edge. If the PERIOD constraint is defined with the attribute HIGH, the initial clock edge is the rising clock edge. If the attribute is LOW, the initial clock edge is the falling clock edge. This can be changed by using the HIGH/LOW keyword in the OFFSET constraint. The OFFSET constraint checks the setup time and hold time. For additional information on timing constraints, please refer to the Constraints Guide at http://www.xilinx.com/support under Documentation, Software Manuals.

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