Create a Logic Allocation File, Generate a Mask File

BitGen Options

–l (Create a Logic Allocation File)

This option creates an ASCII logic allocation file (design.ll) for the selected design. The logic allocation file shows the bitstream position of latches, flip-flops, IOB inputs and outputs, and the bitstream position of LUT programming and Block RAMs.

In some applications, you may want to observe the contents of the FPGA internal registers at different times. The file created by the –l option helps you identify which bits in the current bitstream represent outputs of flip-flops and latches. Bits are referenced by frame and bit number within the frame.

The iMPACT tool uses the design.ll file to locate signal values inside a readback bitstream.

–m (Generate a Mask File)

Creates a mask file. This file determines which bits in the bitstream should be compared to readback data for verification purposes.

–r (Create a Partial Bit File)

–rbit_file

The –r option is used to create a partial bit file. It takes that bit file and compares it to the

.ncd file given to bitgen. Instead of writing out a full bit file, it only writes out the part of the bit file that is different from the original bit file given.

–w (Overwrite Existing Output File)

Enables you to overwrite an existing BitGen output file. See “BitGen Output Files” for additional information.

Development System Reference Guide

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Xilinx 8.2i manual Create a Logic Allocation File, Generate a Mask File, Create a Partial Bit File, Rbitfile

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Contents

Development System Reference Guide Development System Reference Guide About This Guide Guide Contents Preface About This Guide Typographical Additional ResourcesConventions Loc1 loc2 ... locn Online DocumentPreface About This Guide Convention Meaning or Use Example Allow block blockname Table of Contents Tcl PARTGen MAP Logical Design Rule CheckNGDBuild PAR Physical Design Rule Check Development System Reference Guide PIN2UCF XPower Trace Output Files Trace BitGen Speedprint BSDLAnno IBISWriter PROMGen TAEngine CPLDfitTsim NetGen Hprep6 Development System Reference Guide Xflow EDIF2NGD, and NGDBuild Data2MEM Introduction Command Line Program Overview1Command Line Programs in the Design Flow Design Flow Step Introduction Command Line SyntaxCommand Line Options Execute Commands File Help Command Line OptionsSymbol Description Programname -h filename Introduction Symbol DescriptionIntstyle Integration Style Programname -harchitecturename Part Number 2Part Number Examples Specification Introduction 2Part Number Examples Specification Invoking Command Line Programs Design Flow Overview Design Flow Xilinx Design Flow Design Flow 2Xilinx Software Design Flow FPGAs Design Flow Overview 3Xilinx Software Design Flow CPLDs Design Entry and Synthesis Design Entry and SynthesisHierarchical Design Core Generator Tool FPGAs Only Schematic Entry OverviewLibrary Elements Mapping Constraints FPGAs Only HDL Entry and SynthesisFunctional Simulation Constraints Netlist Translation Programs Block PlacementTiming Specifications Design Implementation 5Design Implementation Flow FPGAs Design Implementation 6Design Implementation Flow CPLDs Bitstream Generation FPGAs Only Mapping FPGAs OnlyPlacing and Routing FPGAs Only 1Verification Tools Verification Type Design Verification 7Three Verification Methods of the Design Flow FPGAs Design Verification Back-Annotation Simulation 9Back-Annotation Flow for FPGAs NetGen Schematic-Based Simulation Timing Simulation HDL-Based Simulation 2Five Simulation Points in HDL Design Flow UniSim SimPrim 11Simulation Points for HDL Designs Static Timing Analysis FPGAs Only Probe In-Circuit VerificationDesign Rule Checker FPGAs Only Xilinx Design Download Cables Global Clock Distribution 3Global Clock Resources Fpga Family Number Destination PinsFpga Design Tips Design Size and Performance 12 Gated Clock Data Feedback and Clock Enable Counters 13Synchronous Design Using Data Feedback Q0. . . .Q7Q8. . . .Q15 Other Synchronous Design ConsiderationsQ0. . . .Q7 Q8. . . .Q15 Tcl Overview Tcl Xilinx Tcl Shell Accessing Help Tcl Fundamentals Tcl Fundamentals Xilinx Namespace Xilinx Tcl Commands1Xilinx Tcl Commands for General Usage Subcommands Project create and manage projects Partition support design preservation Tcl Commands for General Usage2Xilinx Tcl Commands for Advanced Scripting Subcommands Partition delete /stopwatch/Instdcm1 Tcl Commands for General UsageDelete delete a partition Get get partition properties Partition new /stopwatch/Instdcm1 New create a new partitionPartition get /stopwatch/Instdcm1 preserve Partition properties Properties list available partition propertiesRerun force partition synthesis and implementation Set set partition preserve property 4Process Tasks Process run and manage project processesRun run process task Project create and manage projects Clean remove system-generated project filesProject clean Project close Close close the ISE projectGet get project properties Getprocesses get project processes Project new watchver.ise New create a new ISE projectOpen open an ISE project Project getprocesses -instance Instdcm1 Project properties -process all Properties list project propertiesSet set project properties, values, and options Project set device xc2vp2 Set device set deviceSet family set device family Project set Map Effort Level high Project set package fg256 Set package set device packageSet speed set device speed Project set family Virtex2p Project set speed Timinganalysis generate timing analysis reportsSet top set the top-level module/entity Delete delete timing analysis Disablecpt disable components for path tracing control Disableconstraints disable timing constraints Ns High 50.00000% Enablecpt enable components for path tracing controlTiminganalysis enableconstraints Stopwatchtiming TSclk=PERIOD TIMEGROUP\sclk\ Regsrclk ureg1 ureg2 ureg3 Timinganalysis enablecpt stopwatchtimingGet get analysis property Ascii New new timing analysis Saveas save analysis report Reset reset path filters and constraintsTiminganalysis reset stopwatchtiming Run run analysis Analysisspeed Set set analysis propertiesSetconstraint set constraint for custom analysis Timinganalysis set stopwatchtiming Period 13 sclk Setendpoints set source and destination endpointsTiminganalysis setconstraint stopwatchtiming Exclude uregnet1 uregnet2 uregnet3 Setquery set up net or timegroup reportSetfilter set filter for analysis Timinganalysis setfilter stopwatchtiming nets Example Showsettings generate settings reportXfile manage project files Add add file to project Xfile get timestamp stopwatch.vhd Get get project file propertiesRemove remove file from project Xfile add *.vhd /mysource/mysubdir timing.ucf Xfile remove stopwatch.vhd Tcl Commands for Advanced ScriptingCollection create and manage a collection Appendto add objects to a collection Set colVar2 $colVar1 Tcl Commands for Advanced ScriptingCopy copy a collection Set colVar1 search * -type instance Collection equal $colVar1 $colVar2 Equal compare two collectionsSet colVar2 collection copy $colVar1 Set colVar2 search /top/T* -type instance Get get collection property Foreach iterate over elements in a collection Object name $item Index extract a collection objectProperties list available collection properties Set item collection index $colVar Collection properties Removefrom remove objects from a collectionSet set the property for all collections Collection sizeof $colVar Object get object informationSizeof show the number of objects in a collection Collection set displaytype true Object properties $obj foreach prop $objProps Get get object propertiesName name of the object Collection foreach obj $colVar set objProps Set colVar search * -type partition Properties list object propertiesObject name collection index $colVar Object type collection index $colVar Search search and return matching objectsType type of object Option Name Synthesis Tool Project Properties and OptionsSearch /stopwatch -type instance 6Project Properties Property Name Description Project Properties and Options NGDBuild Options Option Name Implementation Tool Option Name Implementation Tool Tcl 10 PAR Options Example Tcl Scripts Example Tcl ScriptsSample Tcl Script for General Usage Tcl Sample Tcl Script for Advanced Scripting 100 Partgen options PARTGenPARTGen Overview PARTGen Syntax Arch Print Information for Specified Architecture PARTGen Input FilesPARTGen Output Files PARTGen Options PARTGen Options Print a List of Devices, Packages, and Speeds PARTGen Options 2s400e Xcv400 Device V400bg432 Part Creates Package file and Partlist FilesNopkgfile No Package File Pname Creates Package and Partlist Files Partlist File Part architecture family partname diename packagefilename HeaderDevice Attributes Partlist File Select RAM PKG File PKG File Done Logical DRC Overview Logical Design Rule Check Pad Check Logical DRC ChecksBlock Check Net Check Logical DRC Checks Clock Buffer CheckName Check Primitive Pin Check 1Checked Primitive Pins NGD Primitive Pins Checked NGDBuild Overview NGDBuild 1NGDBuild Design Flow Converting a Netlist to an NGD File Ngdbuild options designname ngdfile.ngd NGDBuild SyntaxNGDBuild Input Files NGDBuild Syntax 120 NGDBuild Options Add PADs to Top-Level Port SignalsNGDBuild Output Files NGDBuild Intermediate Files Ignore UCF File Aul Allow Unmatched LOCsBm Specify BMM Files Dd Destination Directory Synopsys InsertkeephierarchyLibraries to Search NGDBuild Options Usepimmodulename1 -usepimmodulename2 Modular assemble Module AssemblyModular initial Initial Budgeting of Modular Design Modular assemble -pimpath pimdirectorypath Pimcreate pimdirectory -ncd designnamerouted.ncd Modular module Active Module ImplementationNt Netlist Translation Type Modular module -active modulename Allow Unexpanded Blocks Ignore LOC ConstraintsSd Search Specified Directory Uc ucffile.ucf Uc User Constraints FileUr Read User Rules File Verbose Report All Messages 128 MAP Overview MAP Map options infile.ngd pcffile.pcf MAP Syntax MAP Input Files MAP Input FilesMAP Output Files 1Map Options and Architectures MAP Options Cpackfactor Bp Map Slice LogicPack CLBs MAP Options 1Map Options and Architectures Cm area speed balanced Cm Cover ModeDetail Write Out Detailed MAP Report Equivalentregisterremoval Remove Redundant Registers Globalopt Global Optimization Gm Guide ModeGm incremental Guide Mode incremental Gf Guide NCD File Map to Input Functions Ignorekeephierarchy Ignore Keephierarchy PropertiesIr Do Not Use RLOCs to Generate RPMs Ise ISE Project File Output File Name No logic replication Olstdmedhigh Ol Overall Effort Level Retiming Register Retiming During Global Optimization Pr Pack Registers in I/ONo Register Ordering Registerduplication Duplicate Registers Tx on off aggressive limit Timing Timing-Driven Packing and PlacementTx Transform Buses MAP Process MAP ProcessDo Not Remove Unused Logic Xe Extra Effort Level Register Ordering Data01 Addr02 Atod03 Dtoa04 Register Ordering 3Guided Mapping Guided Mapping Simulating Map Results Simulating Map Results 4Logical Circuit Representation MAP Report MRP File MAP Report MRP File 148 Development System Reference Guide 149 Type Block GND Xstgnd IOB 152 Halting MAP Halting MAP 154 DRC Overview Physical Design Rule Check DRC Options DRC SyntaxDRC Input File DRC Output File DRC Checks DRC ChecksReport Incomplete Programming DRC Errors and Warnings Place and Route Overview PAR PAR Flow Timing-driven PAR PAR ProcessPlacing Routing Par -k previous.ncd reentrant.ncd pref.pcf Command Line ExamplesPar input.ncd output.ncd Guided PAR Guided PAR PCI Cores PAR Syntax PAR SyntaxPAR Input Files PAR Output Files Ol value for the router 1Effort Level Options Function Range DefaultGeneral Options Function Range Default PAR Options Existingfile PAR Options 2General Options Function Range DefaultGuide Options Function Range Default Gf Guide NCD File Execute Commands FileDetailed Listing of Options PAR Options Gm Guide ModeIntstyle Integration Style Re-Entrant Routing Ol Overall Effort Level Multi-Tasking ModeNumber of PAR Iterations Nopad No Pad No Routing No PlacementPower Power Aware PAR Pl Placer Effort Level Overwrite Existing Files Number of Results to SaveStarting Placer Cost Table Ub Use Bonded I/Os PAR Reports Performance Evaluation ModePAR Reports Xe Extra Effort Level Place and Route Report File Development System Reference Guide 175 Ing score in parenthesis Development System Reference Guide 177 Par -n 3 -pl high -rl std address.ncd output.dir Multi Pass Place and Route MpprPlacer effort levelrouter effort levelcost table number Multi Pass Place and Route Mppr Select I/O Utilization and Usage SummaryImporting the PAD File Information Guide Reporting Xplorer Best Performance Mode Xplorer Timing Closure ModeXplorer Syntax 5Xplorer Options Function Xplorer Input FilesXplorer Output Files Xplorer Options Xplorer 5Xplorer Options Function Xplorer Report 184 ReportGen Output Files ReportGenReportGen Syntax ReportGen Input Files Padfmt padcsvtxt ReportGen OptionsOption Usage Function Isexflowsilent Par -m nodefilename -ol high -n 10 mydesign.ncd output.dir Turns Engine PAR Multi-Tasking OptionTurns Engine Overview Turns Engine PAR Multi-Tasking Option Turns Engine Input Files Turns Engine Syntax System Requirements Turns Engine Output FilesLimitations Turns Engine Environment Variables Rsh machinename Debugging Screen Output Node Status JOB Time Halting PAR Halting PAR 196 XPower Overview XPower Cpld Designs XPower SyntaxFiles Used by XPower Fpga Designs VCD Data Entry Using XPowerUsing XPower Ls List Supported Devices Rename Power ReportOther Methods of Data Entry Limit Wx Write XML File Specify Settings XML Input FileSpecify VCD file Tb Turn On Time Based Reporting Standard Reports Command Line ExamplesPower Reports Advanced Reports Power ReportsDetailed Reports 204 PIN2UCF Overview PIN2UCF PIN2UCF Flow PIN2UCF Syntax PIN2UCF SyntaxPIN2UCF Input Files PIN2UCF Output Files Outfile.ucf PIN2UCF OptionsPIN2UCF Scenarios Write to a Report File Existing Pinlock section. 210 Trace Overview Trace Trce -runmacro.xtm design.ncd constraint.pcf Trace SyntaxTrace Input Files Trce options design.ncd constraint.pcf Trace Output Files Trace Output FilesInput files to Trace Fastpaths Report Fastest Paths Generate an Error ReportTrace Options Advanced Analysis Trace Options Nodatasheet No Data SheetLimit Timing Report Output Timing Report File Name Skew Run Run Timing Analyzer MacroChange Speed Skew Analyze Clock Skew for All Clocks Ulimit Stamp Generates Stamp timing model filesReport Uncovered Paths Stampstampfile design.ncd Vlimit Trace Command Line ExamplesGenerate a Verbose Report Xml XML Output File Name Trace Reports Trace Reports Net Skew Constraints Net Delay ConstraintsPath Delay Constraints Timing Verification with Trace 1Path Delay Constraint Terminology Definition Clock Skew and Setup Checking 2Clock Skew Example 2Clock Skew and Setup Checking Terminology Terms Definition 3Clock Passing Through Multiple Buffers Reporting with Trace 5Error reporting for failed timing constraints Data Sheet Report Development System Reference Guide 227 BSLOT0 D0S Report Legend Guaranteed Setup and Hold Reporting Hold Times Setup Times Trce -o summary.twr ramb16s1.ncd Summary Report Without a Physical Constraints File Specified Trce -o summary1.twr ramb16s1.ncd clkperiod.pcf Development System Reference Guide 233 Trce -e 3 ramb16s1.ncd clkperiod.pcf -o errorreport.twr Development System Reference Guide 235 236 Development System Reference Guide 237 BUFGMUX.I0 Offset Constraints Offset Constraints Offset in Path Details Offset in Constraint ExamplesOffset in Header Offset in Detailed Path Data Offset in Detail Path Clock Path Offset In with Phase Shifted Clock Development System Reference Guide 243 Offset OUT Header Offset OUT Constraint Examples Offset OUT Detail Clock Path Offset OUT Path Details Offset OUT Detail Path Data Period Constraints Period ConstraintsPeriod Constraints Examples Period Header Period Path Period Path Details Period Constraint with Phase Period Path with Phase Minimum Period Statistics Halting Trace Speedprint Overview Speedprint Min Display Minimum Speed Data Specify TemperatureSpeedprint Syntax Speedprint Options Speedprint Example Reports Speedprint Example CommandsSpeedprint Example Commands Command Description Lvttl Fast BitGen Overview BitGen Loutfilename.ll Moutfilename.msk Boutfilename.rbt BitGen SyntaxOption Output File BitGen Input Files BitGen Input FilesBitGen Output Files Create Rawbits File BitGen Options Do Not Run DRC Bd Update Block RamsSet Configuration Bitgen -goptionsetting design.ncd design.bit design.pcf CclkPin ActiveReconfigActivateGCLK Binary Compress ConfigRate DebugBitstream DCIUpdateModeDCMShutdown DonePipe DisableBandgapDONEcycle DonePin GSRcycle DriveDoneEncrypt Gclkdel0, Gclkdel1, Gclkdel2, Gclkdel3 Key0, Key1, Key2, Key3, Key4, Key5 GWEcycleGTScycle HswapenPin M0Pin KeyFileKeyseq0, Keyseq1, Keyseq2, Keyseq3, Keyseq4, Keyseq5 LCKcycle PartialGCLK M1PinM2Pin Matchcycle Persist PartialMask0, PartialMask1, PartialMask2PartialLeft PartialRight Security PowerdownPinProgPin ReadBack StartupClk SEURepairStartCBC StartKey TmsPin TckPinTdiPin TdoPin UserID No BIT FileUnusedPin Overwrite Existing Output File Create a Logic Allocation FileGenerate a Mask File Create a Partial Bit File 276 BSDLAnno Overview BSDLAnno BSDLAnno Options BSDLAnno SyntaxBSDLAnno Input Files BSDLAnno Output Files BSDLAnno File Composition BSDLAnno File CompositionEntity Declaration Generic Parameter Package Pin-Mapping Logical Port Description TAP Description USE StatementScan Port Identification Boundary Register Description Bsdl File Modifications for Single-Ended Pins Explanation BSDLAnno BSDLAnno version number Boundary Scan Behavior in Xilinx DevicesModifications to the Designwarning Section Header Comments PROMGen Overview PROMGen Promgen options PROMGen SyntaxPROMGen Input Files PROMGen Output Files PROMGen Options File1.bit file2.bit Add BIT FIlesProm Format Load Prom File Ver Version Prom SizeTemplate File Load Upward Bit Swapping in Prom Files Enable Compression PROMGen Examples PROMGen Examples 292 IBISWriter Overview IBISWriter Ibiswriter options infile outfile.ibs IBISWriter Syntax Set Reference Voltage IBISWriter Input FilesIBISWriter Output Files IBISWriter Options Architecture Option Value Description Ml Multilingual Support IBISWriter Options Pin Generate Package Parasitics 298 CPLDfit Overview CPLDfit CPLDfit Output Files CPLDfit SyntaxCPLDfit Input Files CPLDfit Options Loc Keep Specified Location Constraints Inputs Number of Inputs to Use During OptimizationIostd Specify I/O Standard Keepio Prevent Optimization of Unused Inputs Nogtsopt Disable Global Output-Enable Optimization Nofbnand Disable Use of Foldback NandsNogclkopt Disable Global Clock Optimization Nogsropt Disable Global Set/Reset Optimization Pinfbk Use Pin Feedback Power Set Power ModeOptimize Optimize Logic for Density or Speed Specify Xilinx Part Wysiwyg Do Not Perform Optimization Terminate Set to Termination ModeUnused Set Termination Mode of Unused I/Os Slew Set Slew Rate 306 Tsim Syntax Tsim Tsim Input Files TAEngine Overview TAEngine 1TAEngine Design Flow TAEngine Syntax Specify Output Filename TAEngine OptionsDetail Detail Report Iopath Trace Paths 312 1Hprep6 Design Flow Hprep6 Autosig Automatically Generate Signature Hprep6 SyntaxHprep6 Options Tmv Specify Test Vector File Nopullup Disable PullupsSpecify Signature Value for Readback Produce ISC File 316 NetGen Overview NetGen 1NetGen Output File Types Input Design File NetGen NetGen Simulation Flow NetGen Simulation FlowNetGen Functional Simulation Flow NetGen Supported Flows Ngcbuildoptions toplevelnetlistfile outputngcfile NetGen Timing Simulation FlowSyntax for NetGen Functional Simulation Output files for NetGen Functional Simulation NetGen Timing Simulation Flow Syntax for NetGen Timing SimulationFpga Timing Simulation Output files for Cpld Timing Simulation Output files for Fpga Timing SimulationCpld Timing Simulation Input files for Cpld Timing Simulation Options for NetGen Simulation Flow Module Simulation of Active Module Insertppbuffers Insert Path Pulse BuffersMhf Multiple Hierarchical Files Sim Generate Simulation Netlist Ofmt Output FormatPcf PCF File Change Speed Insertglbl Insert glbl.v Module Ti Top Instance NameTm Top Module Name Tp Bring Out Global 3-State Net as Port Sdfpath Full Path to SDF File Ne No Name EscapingPf Generate PIN File Sdfanno Include $sdfannotate VHDL-Specific Options for Functional and Timing Simulation Xon truefalse NetGen Equivalence Checking FlowXon Select Output Behavior for Timing Violations NetGen Equivalence Checking Flow Input files for NetGen Equivalence Checking Syntax for NetGen Equivalence Checking Ecn Equivalence Checking Output files for NetGen Equivalence CheckingOptions for NetGen Equivalence Checking Flow Module Verification of Active Module NetGen Static Timing Analysis Flow NetGen Static Timing Analysis FlowNgm Design Correlation File Syntax for NetGen Static Timing Analysis Input files for Static Timing AnalysisOutput files for Static Timing Analysis Options for NetGen Static Timing Analysis Flow 336 Modulename .sim Modulename .ecn Modulename .sta Preserving and Writing Hierarchy FilesSta Generate Static Timing Analysis Netlist Preserving and Writing Hierarchy Files Hierarchy Information File Dedicated Global Signals in Back-Annotation SimulationTestbench File Dedicated Global Signals in Back-Annotation Simulation Global Signals in Verilog NetlistGlobal Signals in Vhdl Netlist 340 Xflow Overview Xflow 1XFLOW Design Flow Xflow Syntax Xflow Input Files Xflow Input Files Xflow Output Files 1XFLOW Output Files FPGAs and CPLDs Xflow Output Files 2XFLOW Output Files FPGAs 3XFLOW Output Files CPLDs Assemble Module AssemblyXflow Flow Types Xflow Flow Types 4Option Files for -assemble Flow Type Description Config Create a BIT File for FPGAsConfigoptionfile Ecn Create a File for Equivalence Checking 6Option Files for -fit Flow Type Description Fit Fit a CpldFsim Create a File for Functional Simulation 5Option Files for -ecn Flow Type Description Implement optionfile Implement Implement an Fpga7Option Files for -fsim Flow Type Xflow -p xc2v250fg256-5 -fsim genericverilog.opt testclk.v Xflow -p xc2v250fg256-5 -initial budget.opt top.edf Initial Initial Budgeting of Modular DesignXflow Flow Types 8Option Files for -implement Flow Type Initial budget.opt 9Option Files for -module Flow Type Module Active Module ImplementationModuleoptionfile -activemodulename 11Option Files for -sta Flow Type Description Mppr Multi-Pass Place and Route for FPGAsSta Create a File for Static Timing Analysis 10Option Files for -mppr Flow Type Description Synthoptionfile SynthSynthesis Types Testclk.prj Tsim Create a File for Timing SimulationOption Files for -synth Flow Types 12Option Files for -synth Flow Type Description 13Option Files for -tsim Flow Type Description Flow Files Fpga Flow File Format Reports Flag Enabled DisabledTriggers Exports End Program programname User Command Blocks Option File Format Xflow Option Files Specify a Global Variable Xflow OptionsActive Active Module Ed Copy Files to Export Directory Xflow -implement balanced.opt -o newname testclk.edf Norun Creates a Script File OnlyChange Output File Name Ooutputfilename Rdreportdirectory Pd PIMs DirectoryRd Copy Report Files Pdpimdirectory Running Smart Flow Using Xflow Flow Types in CombinationRunning Xflow Wd Specify a Working Directory Running Xflow Using the SCR, BAT, or TCL FileUsing the Xilxflowpath Environment Variable 366 Data2MEM Overview Data2MEM Executable and Linkable Format .elf files Data2MEM SyntaxData2MEM Input and Output Files Block RAM Memory Map .bmm files Verilog .v files Debugging Information Format Dwarf .drf filesMemory .mem files Bit .bit files UCF .ucf files 1Data2MEM Command Line Options DescriptionData2MEM Options Vhdl .vhd files Data2MEM Options 1Data2MEM Command Line Options Pp filename Name Type Produced By Description Xilinx Development System Files Appendix MOD Ascii Trace NKY TCL Ascii 378 EDIF2NGD EDIF2NGD, and NGDBuild EDIF2NGD Design Flow Edif2ngd options ediffile ngofile EDIF2NGD SyntaxEDIF2NGD Input Files EDIF2NGD Output Files Aul Allow Unmatched LOCs Add PADs to Top-Level Port SignalsEDIF2NGD Options Llibname Libraries to SearchPart Number Ignore LOC Constraints NGDBuild and the Netlist Readers NGDBuild NGDBuild Busnameindex DI3 Netlist Launcher NetlisterBus Matching Bus Naming Conventions Netlist Launcher Netlister User Rules Format Netlist Launcher Rules FilesUser Rules File User Rules and System Rules Development System Reference Guide 389 Value Types in Key Statements System Rules File Example 1 Edfrule System Rule Rules File Examples Example 3 User Rule Example 2 User Rule NGDBuild File Names and Locations NGDBuild File Names and LocationsExample 4 User Rule 394 Abel Glossary Asic Boundary scan BitstreamBlock Bonded CAE Buft Cmos CLB Compiler ConfigurationContention Combinatorial logic Dangling net CpldDaisy chain Dangling bus DSP DRC Edif EDA Fifo EpromFdsd Fpga Fmap Global 3-state net Global Set/Reset netGate array Global buffers Ibuf HDL IFD Ieee Jedec LSB MSB NGM NCD PAL PLD PIM RAM Prom RTL ROMRPM Startup symbol SDF standard delay formatSet/reset Signal TCL Tsim Trace TTL Xtclsh WireVhdl Vital 422