Design Verification

Design verification procedures should occur throughout your design process, as shown in the following figures.

Simulation
Input Stimulus		Basic Design Flow
		Basic Design Flow
	Integrated Tool	Design Entry
Simulation		Design Entry
	Functional Simulator
	Paths
Simulation Netlist	Translate to	NGD
Simulation Netlist	Simulator Format	NGD
	Simulator Format
Translate to		Mapping, Placement
Simulator Format		Mapping, Placement
Simulator Format		and Routing
		and Routing
Timing Simulation Path			Static Timing
Timing Simulation Path
	Translation	NCD	Static Timing Analysis
		BitGen
			In-Circuit Verification
	Back-Annotation
		BIT	In-Circuit Verification
	NGA
		Xilinx FPGA
			X9556

Figure 2-7:Three Verification Methods of the Design Flow (FPGAs)

Development System Reference Guide

www.xilinx.com

Page 41

Image 41

Xilinx 8.2i manual Design Verification, 7Three Verification Methods of the Design Flow FPGAs

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Contents

Development System Reference Guide Development System Reference Guide About This Guide Guide Contents Preface About This Guide Typographical Additional ResourcesConventions Preface About This Guide Convention Meaning or Use Example Online DocumentAllow block blockname Loc1 loc2 ... locn Table of Contents Tcl PARTGen MAP Logical Design Rule CheckNGDBuild PAR Physical Design Rule Check Development System Reference Guide PIN2UCF XPower Trace Output Files Trace BitGen Speedprint BSDLAnno IBISWriter PROMGen TAEngine CPLDfitTsim NetGen Hprep6 Development System Reference Guide Xflow EDIF2NGD, and NGDBuild Data2MEM Introduction Command Line Program Overview1Command Line Programs in the Design Flow Design Flow Step Command Line Options Command Line SyntaxExecute Commands File Introduction Help Command Line OptionsSymbol Description Intstyle Integration Style Introduction Symbol DescriptionProgramname -harchitecturename Programname -h filename Part Number 2Part Number Examples Specification Introduction 2Part Number Examples Specification Invoking Command Line Programs Design Flow Overview Design Flow Xilinx Design Flow Design Flow 2Xilinx Software Design Flow FPGAs Design Flow Overview 3Xilinx Software Design Flow CPLDs Design Entry and Synthesis Design Entry and SynthesisHierarchical Design Core Generator Tool FPGAs Only Schematic Entry OverviewLibrary Elements Functional Simulation HDL Entry and SynthesisConstraints Mapping Constraints FPGAs Only Timing Specifications Block PlacementDesign Implementation Netlist Translation Programs 5Design Implementation Flow FPGAs Design Implementation 6Design Implementation Flow CPLDs Bitstream Generation FPGAs Only Mapping FPGAs OnlyPlacing and Routing FPGAs Only 1Verification Tools Verification Type Design Verification 7Three Verification Methods of the Design Flow FPGAs Design Verification Back-Annotation Simulation 9Back-Annotation Flow for FPGAs NetGen Schematic-Based Simulation Timing Simulation HDL-Based Simulation 2Five Simulation Points in HDL Design Flow UniSim SimPrim 11Simulation Points for HDL Designs Static Timing Analysis FPGAs Only Design Rule Checker FPGAs Only In-Circuit VerificationXilinx Design Download Cables Probe Fpga Design Tips 3Global Clock Resources Fpga Family Number Destination PinsDesign Size and Performance Global Clock Distribution 12 Gated Clock Data Feedback and Clock Enable Counters 13Synchronous Design Using Data Feedback Q0. . . .Q7Q8. . . .Q15 Other Synchronous Design ConsiderationsQ0. . . .Q7 Q8. . . .Q15 Tcl Overview Tcl Xilinx Tcl Shell Accessing Help Tcl Fundamentals Tcl Fundamentals Xilinx Namespace Xilinx Tcl Commands1Xilinx Tcl Commands for General Usage Subcommands Project create and manage projects Partition support design preservation Tcl Commands for General Usage2Xilinx Tcl Commands for Advanced Scripting Subcommands Delete delete a partition Tcl Commands for General UsageGet get partition properties Partition delete /stopwatch/Instdcm1 Partition new /stopwatch/Instdcm1 New create a new partitionPartition get /stopwatch/Instdcm1 preserve Partition properties Properties list available partition propertiesRerun force partition synthesis and implementation Set set partition preserve property 4Process Tasks Process run and manage project processesRun run process task Project create and manage projects Clean remove system-generated project filesProject clean Get get project properties Close close the ISE projectGetprocesses get project processes Project close Open open an ISE project New create a new ISE projectProject getprocesses -instance Instdcm1 Project new watchver.ise Project properties -process all Properties list project propertiesSet set project properties, values, and options Set family set device family Set device set deviceProject set Map Effort Level high Project set device xc2vp2 Set speed set device speed Set package set device packageProject set family Virtex2p Project set package fg256 Set top set the top-level module/entity Timinganalysis generate timing analysis reportsDelete delete timing analysis Project set speed Disablecpt disable components for path tracing control Disableconstraints disable timing constraints Timinganalysis enableconstraints Enablecpt enable components for path tracing controlStopwatchtiming TSclk=PERIOD TIMEGROUP\sclk\ Ns High 50.00000% Regsrclk ureg1 ureg2 ureg3 Timinganalysis enablecpt stopwatchtimingGet get analysis property Ascii New new timing analysis Timinganalysis reset stopwatchtiming Reset reset path filters and constraintsRun run analysis Saveas save analysis report Setconstraint set constraint for custom analysis Set set analysis propertiesTiminganalysis set stopwatchtiming Analysisspeed Period 13 sclk Setendpoints set source and destination endpointsTiminganalysis setconstraint stopwatchtiming Setfilter set filter for analysis Setquery set up net or timegroup reportTiminganalysis setfilter stopwatchtiming nets Exclude uregnet1 uregnet2 uregnet3 Xfile manage project files Showsettings generate settings reportAdd add file to project Example Remove remove file from project Get get project file propertiesXfile add *.vhd /mysource/mysubdir timing.ucf Xfile get timestamp stopwatch.vhd Collection create and manage a collection Tcl Commands for Advanced ScriptingAppendto add objects to a collection Xfile remove stopwatch.vhd Copy copy a collection Tcl Commands for Advanced ScriptingSet colVar1 search * -type instance Set colVar2 $colVar1 Set colVar2 collection copy $colVar1 Equal compare two collectionsSet colVar2 search /top/T* -type instance Collection equal $colVar1 $colVar2 Get get collection property Foreach iterate over elements in a collection Properties list available collection properties Index extract a collection objectSet item collection index $colVar Object name $item Collection properties Removefrom remove objects from a collectionSet set the property for all collections Sizeof show the number of objects in a collection Object get object informationCollection set displaytype true Collection sizeof $colVar Name name of the object Get get object propertiesCollection foreach obj $colVar set objProps Object properties $obj foreach prop $objProps Set colVar search * -type partition Properties list object propertiesObject name collection index $colVar Object type collection index $colVar Search search and return matching objectsType type of object Search /stopwatch -type instance Project Properties and Options6Project Properties Property Name Description Option Name Synthesis Tool Project Properties and Options NGDBuild Options Option Name Implementation Tool Option Name Implementation Tool Tcl 10 PAR Options Example Tcl Scripts Example Tcl ScriptsSample Tcl Script for General Usage Tcl Sample Tcl Script for Advanced Scripting 100 PARTGen Overview PARTGenPARTGen Syntax Partgen options PARTGen Output Files PARTGen Input FilesPARTGen Options Arch Print Information for Specified Architecture PARTGen Options Print a List of Devices, Packages, and Speeds PARTGen Options 2s400e Nopkgfile No Package File Creates Package file and Partlist FilesPname Xcv400 Device V400bg432 Part Creates Package and Partlist Files Partlist File Device Attributes HeaderPartlist File Part architecture family partname diename packagefilename Select RAM PKG File PKG File Done Logical DRC Overview Logical Design Rule Check Block Check Logical DRC ChecksNet Check Pad Check Logical DRC Checks Clock Buffer CheckName Check Primitive Pin Check 1Checked Primitive Pins NGD Primitive Pins Checked NGDBuild Overview NGDBuild 1NGDBuild Design Flow Converting a Netlist to an NGD File NGDBuild Input Files NGDBuild SyntaxNGDBuild Syntax Ngdbuild options designname ngdfile.ngd 120 NGDBuild Output Files Add PADs to Top-Level Port SignalsNGDBuild Intermediate Files NGDBuild Options Bm Specify BMM Files Aul Allow Unmatched LOCsDd Destination Directory Ignore UCF File Libraries to Search InsertkeephierarchyNGDBuild Options Synopsys Modular initial Initial Budgeting of Modular Design Modular assemble Module AssemblyModular assemble -pimpath pimdirectorypath Usepimmodulename1 -usepimmodulename2 Nt Netlist Translation Type Modular module Active Module ImplementationModular module -active modulename Pimcreate pimdirectory -ncd designnamerouted.ncd Allow Unexpanded Blocks Ignore LOC ConstraintsSd Search Specified Directory Ur Read User Rules File Uc User Constraints FileVerbose Report All Messages Uc ucffile.ucf 128 MAP Overview MAP Map options infile.ngd pcffile.pcf MAP Syntax MAP Input Files MAP Input FilesMAP Output Files 1Map Options and Architectures MAP Options Pack CLBs Bp Map Slice LogicMAP Options 1Map Options and Architectures Cpackfactor Detail Write Out Detailed MAP Report Cm Cover ModeEquivalentregisterremoval Remove Redundant Registers Cm area speed balanced Gm incremental Guide Mode incremental Gm Guide ModeGf Guide NCD File Globalopt Global Optimization Ir Do Not Use RLOCs to Generate RPMs Ignorekeephierarchy Ignore Keephierarchy PropertiesIse ISE Project File Map to Input Functions Output File Name No logic replication Olstdmedhigh Ol Overall Effort Level No Register Ordering Pr Pack Registers in I/ORegisterduplication Duplicate Registers Retiming Register Retiming During Global Optimization Tx on off aggressive limit Timing Timing-Driven Packing and PlacementTx Transform Buses Do Not Remove Unused Logic MAP ProcessXe Extra Effort Level MAP Process Register Ordering Data01 Addr02 Atod03 Dtoa04 Register Ordering 3Guided Mapping Guided Mapping Simulating Map Results Simulating Map Results 4Logical Circuit Representation MAP Report MRP File MAP Report MRP File 148 Development System Reference Guide 149 Type Block GND Xstgnd IOB 152 Halting MAP Halting MAP 154 DRC Overview Physical Design Rule Check DRC Input File DRC SyntaxDRC Output File DRC Options DRC Checks DRC ChecksReport Incomplete Programming DRC Errors and Warnings Place and Route Overview PAR PAR Flow Placing PAR ProcessRouting Timing-driven PAR Par -k previous.ncd reentrant.ncd pref.pcf Command Line ExamplesPar input.ncd output.ncd Guided PAR Guided PAR PCI Cores PAR Input Files PAR SyntaxPAR Output Files PAR Syntax General Options Function Range Default 1Effort Level Options Function Range DefaultPAR Options Ol value for the router Existingfile PAR Options 2General Options Function Range DefaultGuide Options Function Range Default Gf Guide NCD File Execute Commands FileDetailed Listing of Options Intstyle Integration Style Gm Guide ModeRe-Entrant Routing PAR Options Number of PAR Iterations Multi-Tasking ModeNopad No Pad Ol Overall Effort Level Power Power Aware PAR No PlacementPl Placer Effort Level No Routing Starting Placer Cost Table Number of Results to SaveUb Use Bonded I/Os Overwrite Existing Files PAR Reports Performance Evaluation ModeXe Extra Effort Level PAR Reports Place and Route Report File Development System Reference Guide 175 Ing score in parenthesis Development System Reference Guide 177 Par -n 3 -pl high -rl std address.ncd output.dir Multi Pass Place and Route MpprPlacer effort levelrouter effort levelcost table number Importing the PAD File Information Select I/O Utilization and Usage SummaryGuide Reporting Multi Pass Place and Route Mppr Xplorer Best Performance Mode Xplorer Timing Closure ModeXplorer Syntax Xplorer Output Files Xplorer Input FilesXplorer Options 5Xplorer Options Function Xplorer 5Xplorer Options Function Xplorer Report 184 ReportGen Syntax ReportGenReportGen Input Files ReportGen Output Files Option Usage Function ReportGen OptionsIsexflowsilent Padfmt padcsvtxt Turns Engine Overview Turns Engine PAR Multi-Tasking OptionTurns Engine PAR Multi-Tasking Option Par -m nodefilename -ol high -n 10 mydesign.ncd output.dir Turns Engine Input Files Turns Engine Syntax System Requirements Turns Engine Output FilesLimitations Turns Engine Environment Variables Rsh machinename Debugging Screen Output Node Status JOB Time Halting PAR Halting PAR 196 XPower Overview XPower Files Used by XPower XPower SyntaxFpga Designs Cpld Designs VCD Data Entry Using XPowerUsing XPower Other Methods of Data Entry Rename Power ReportLimit Ls List Supported Devices Specify VCD file Specify Settings XML Input FileTb Turn On Time Based Reporting Wx Write XML File Standard Reports Command Line ExamplesPower Reports Advanced Reports Power ReportsDetailed Reports 204 PIN2UCF Overview PIN2UCF PIN2UCF Flow PIN2UCF Input Files PIN2UCF SyntaxPIN2UCF Output Files PIN2UCF Syntax PIN2UCF Scenarios PIN2UCF OptionsWrite to a Report File Outfile.ucf Existing Pinlock section. 210 Trace Overview Trace Trace Input Files Trace SyntaxTrce options design.ncd constraint.pcf Trce -runmacro.xtm design.ncd constraint.pcf Trace Output Files Trace Output FilesInput files to Trace Trace Options Generate an Error ReportAdvanced Analysis Fastpaths Report Fastest Paths Limit Timing Report Nodatasheet No Data SheetOutput Timing Report File Name Trace Options Change Speed Run Run Timing Analyzer MacroSkew Analyze Clock Skew for All Clocks Skew Report Uncovered Paths Stamp Generates Stamp timing model filesStampstampfile design.ncd Ulimit Generate a Verbose Report Trace Command Line ExamplesXml XML Output File Name Vlimit Trace Reports Trace Reports Path Delay Constraints Net Delay ConstraintsTiming Verification with Trace Net Skew Constraints 1Path Delay Constraint Terminology Definition Clock Skew and Setup Checking 2Clock Skew Example 2Clock Skew and Setup Checking Terminology Terms Definition 3Clock Passing Through Multiple Buffers Reporting with Trace 5Error reporting for failed timing constraints Data Sheet Report Development System Reference Guide 227 BSLOT0 D0S Report Legend Guaranteed Setup and Hold Reporting Hold Times Setup Times Trce -o summary.twr ramb16s1.ncd Summary Report Without a Physical Constraints File Specified Trce -o summary1.twr ramb16s1.ncd clkperiod.pcf Development System Reference Guide 233 Trce -e 3 ramb16s1.ncd clkperiod.pcf -o errorreport.twr Development System Reference Guide 235 236 Development System Reference Guide 237 BUFGMUX.I0 Offset Constraints Offset Constraints Offset in Path Details Offset in Constraint ExamplesOffset in Header Offset in Detailed Path Data Offset in Detail Path Clock Path Offset In with Phase Shifted Clock Development System Reference Guide 243 Offset OUT Header Offset OUT Constraint Examples Offset OUT Detail Clock Path Offset OUT Path Details Offset OUT Detail Path Data Period Constraints Examples Period ConstraintsPeriod Header Period Constraints Period Path Period Path Details Period Constraint with Phase Period Path with Phase Minimum Period Statistics Halting Trace Speedprint Overview Speedprint Speedprint Syntax Specify TemperatureSpeedprint Options Min Display Minimum Speed Data Speedprint Example Commands Speedprint Example CommandsCommand Description Speedprint Example Reports Lvttl Fast BitGen Overview BitGen Loutfilename.ll Moutfilename.msk Boutfilename.rbt BitGen SyntaxOption Output File BitGen Input Files BitGen Input FilesBitGen Output Files Create Rawbits File BitGen Options Set Configuration Bd Update Block RamsBitgen -goptionsetting design.ncd design.bit design.pcf Do Not Run DRC ActivateGCLK ActiveReconfigBinary CclkPin Compress ConfigRate DebugBitstream DCIUpdateModeDCMShutdown DONEcycle DisableBandgapDonePin DonePipe Encrypt DriveDoneGclkdel0, Gclkdel1, Gclkdel2, Gclkdel3 GSRcycle GTScycle GWEcycleHswapenPin Key0, Key1, Key2, Key3, Key4, Key5 Keyseq0, Keyseq1, Keyseq2, Keyseq3, Keyseq4, Keyseq5 KeyFileLCKcycle M0Pin M2Pin M1PinMatchcycle PartialGCLK PartialLeft PartialMask0, PartialMask1, PartialMask2PartialRight Persist ProgPin PowerdownPinReadBack Security StartCBC SEURepairStartKey StartupClk TdiPin TckPinTdoPin TmsPin UserID No BIT FileUnusedPin Generate a Mask File Create a Logic Allocation FileCreate a Partial Bit File Overwrite Existing Output File 276 BSDLAnno Overview BSDLAnno BSDLAnno Input Files BSDLAnno SyntaxBSDLAnno Output Files BSDLAnno Options Entity Declaration BSDLAnno File CompositionGeneric Parameter BSDLAnno File Composition Package Pin-Mapping Logical Port Description TAP Description USE StatementScan Port Identification Boundary Register Description Bsdl File Modifications for Single-Ended Pins Explanation Modifications to the Designwarning Section Boundary Scan Behavior in Xilinx DevicesHeader Comments BSDLAnno BSDLAnno version number PROMGen Overview PROMGen PROMGen Input Files PROMGen SyntaxPROMGen Output Files Promgen options PROMGen Options Prom Format Add BIT FIlesLoad Prom File File1.bit file2.bit Template File Prom SizeLoad Upward Ver Version Bit Swapping in Prom Files Enable Compression PROMGen Examples PROMGen Examples 292 IBISWriter Overview IBISWriter Ibiswriter options infile outfile.ibs IBISWriter Syntax IBISWriter Output Files IBISWriter Input FilesIBISWriter Options Set Reference Voltage Architecture Option Value Description Ml Multilingual Support IBISWriter Options Pin Generate Package Parasitics 298 CPLDfit Overview CPLDfit CPLDfit Output Files CPLDfit SyntaxCPLDfit Input Files CPLDfit Options Iostd Specify I/O Standard Inputs Number of Inputs to Use During OptimizationKeepio Prevent Optimization of Unused Inputs Loc Keep Specified Location Constraints Nogclkopt Disable Global Clock Optimization Nofbnand Disable Use of Foldback NandsNogsropt Disable Global Set/Reset Optimization Nogtsopt Disable Global Output-Enable Optimization Optimize Optimize Logic for Density or Speed Power Set Power ModeSpecify Xilinx Part Pinfbk Use Pin Feedback Unused Set Termination Mode of Unused I/Os Terminate Set to Termination ModeSlew Set Slew Rate Wysiwyg Do Not Perform Optimization 306 Tsim Syntax Tsim Tsim Input Files TAEngine Overview TAEngine 1TAEngine Design Flow TAEngine Syntax Detail Detail Report TAEngine OptionsIopath Trace Paths Specify Output Filename 312 1Hprep6 Design Flow Hprep6 Autosig Automatically Generate Signature Hprep6 SyntaxHprep6 Options Specify Signature Value for Readback Nopullup Disable PullupsProduce ISC File Tmv Specify Test Vector File 316 NetGen Overview NetGen 1NetGen Output File Types Input Design File NetGen NetGen Functional Simulation Flow NetGen Simulation FlowNetGen Supported Flows NetGen Simulation Flow Syntax for NetGen Functional Simulation NetGen Timing Simulation FlowOutput files for NetGen Functional Simulation Ngcbuildoptions toplevelnetlistfile outputngcfile NetGen Timing Simulation Flow Syntax for NetGen Timing SimulationFpga Timing Simulation Cpld Timing Simulation Output files for Fpga Timing SimulationInput files for Cpld Timing Simulation Output files for Cpld Timing Simulation Options for NetGen Simulation Flow Module Simulation of Active Module Insertppbuffers Insert Path Pulse BuffersMhf Multiple Hierarchical Files Pcf PCF File Ofmt Output FormatChange Speed Sim Generate Simulation Netlist Tm Top Module Name Ti Top Instance NameTp Bring Out Global 3-State Net as Port Insertglbl Insert glbl.v Module Pf Generate PIN File Ne No Name EscapingSdfanno Include $sdfannotate Sdfpath Full Path to SDF File VHDL-Specific Options for Functional and Timing Simulation Xon Select Output Behavior for Timing Violations NetGen Equivalence Checking FlowNetGen Equivalence Checking Flow Xon truefalse Input files for NetGen Equivalence Checking Syntax for NetGen Equivalence Checking Ecn Equivalence Checking Output files for NetGen Equivalence CheckingOptions for NetGen Equivalence Checking Flow Module Verification of Active Module NetGen Static Timing Analysis Flow NetGen Static Timing Analysis FlowNgm Design Correlation File Syntax for NetGen Static Timing Analysis Input files for Static Timing AnalysisOutput files for Static Timing Analysis Options for NetGen Static Timing Analysis Flow 336 Sta Generate Static Timing Analysis Netlist Preserving and Writing Hierarchy FilesPreserving and Writing Hierarchy Files Modulename .sim Modulename .ecn Modulename .sta Hierarchy Information File Dedicated Global Signals in Back-Annotation SimulationTestbench File Dedicated Global Signals in Back-Annotation Simulation Global Signals in Verilog NetlistGlobal Signals in Vhdl Netlist 340 Xflow Overview Xflow 1XFLOW Design Flow Xflow Syntax Xflow Input Files Xflow Input Files Xflow Output Files 1XFLOW Output Files FPGAs and CPLDs Xflow Output Files 2XFLOW Output Files FPGAs Xflow Flow Types Assemble Module AssemblyXflow Flow Types 3XFLOW Output Files CPLDs Configoptionfile Config Create a BIT File for FPGAsEcn Create a File for Equivalence Checking 4Option Files for -assemble Flow Type Description Fsim Create a File for Functional Simulation Fit Fit a Cpld5Option Files for -ecn Flow Type Description 6Option Files for -fit Flow Type Description 7Option Files for -fsim Flow Type Implement Implement an FpgaXflow -p xc2v250fg256-5 -fsim genericverilog.opt testclk.v Implement optionfile Xflow Flow Types 8Option Files for -implement Flow Type Initial Initial Budgeting of Modular DesignInitial budget.opt Xflow -p xc2v250fg256-5 -initial budget.opt top.edf 9Option Files for -module Flow Type Module Active Module ImplementationModuleoptionfile -activemodulename Sta Create a File for Static Timing Analysis Mppr Multi-Pass Place and Route for FPGAs10Option Files for -mppr Flow Type Description 11Option Files for -sta Flow Type Description Synthoptionfile SynthSynthesis Types Option Files for -synth Flow Types Tsim Create a File for Timing Simulation12Option Files for -synth Flow Type Description Testclk.prj 13Option Files for -tsim Flow Type Description Flow Files Fpga Flow File Format Triggers Flag Enabled DisabledExports Reports End Program programname User Command Blocks Option File Format Xflow Option Files Active Active Module Xflow OptionsEd Copy Files to Export Directory Specify a Global Variable Change Output File Name Norun Creates a Script File OnlyOoutputfilename Xflow -implement balanced.opt -o newname testclk.edf Rd Copy Report Files Pd PIMs DirectoryPdpimdirectory Rdreportdirectory Running Xflow Using Xflow Flow Types in CombinationWd Specify a Working Directory Running Smart Flow Running Xflow Using the SCR, BAT, or TCL FileUsing the Xilxflowpath Environment Variable 366 Data2MEM Overview Data2MEM Data2MEM Input and Output Files Data2MEM SyntaxBlock RAM Memory Map .bmm files Executable and Linkable Format .elf files Memory .mem files Debugging Information Format Dwarf .drf filesBit .bit files Verilog .v files Data2MEM Options 1Data2MEM Command Line Options DescriptionVhdl .vhd files UCF .ucf files Data2MEM Options 1Data2MEM Command Line Options Pp filename Name Type Produced By Description Xilinx Development System Files Appendix MOD Ascii Trace NKY TCL Ascii 378 EDIF2NGD EDIF2NGD, and NGDBuild EDIF2NGD Design Flow EDIF2NGD Input Files EDIF2NGD SyntaxEDIF2NGD Output Files Edif2ngd options ediffile ngofile Aul Allow Unmatched LOCs Add PADs to Top-Level Port SignalsEDIF2NGD Options Part Number Libraries to SearchIgnore LOC Constraints Llibname NGDBuild and the Netlist Readers NGDBuild NGDBuild Bus Matching Netlist Launcher NetlisterBus Naming Conventions Busnameindex DI3 Netlist Launcher Netlister User Rules File Netlist Launcher Rules FilesUser Rules and System Rules User Rules Format Development System Reference Guide 389 Value Types in Key Statements System Rules File Example 1 Edfrule System Rule Rules File Examples Example 3 User Rule Example 2 User Rule NGDBuild File Names and Locations NGDBuild File Names and LocationsExample 4 User Rule 394 Abel Glossary Asic Block BitstreamBonded Boundary scan CAE Buft Cmos CLB Contention ConfigurationCombinatorial logic Compiler Daisy chain CpldDangling bus Dangling net DSP DRC Edif EDA Fifo EpromFdsd Fpga Fmap Gate array Global Set/Reset netGlobal buffers Global 3-state net Ibuf HDL IFD Ieee Jedec LSB MSB NGM NCD PAL PLD PIM RAM Prom RTL ROMRPM Set/reset SDF standard delay formatSignal Startup symbol TCL Tsim Trace TTL Vhdl WireVital Xtclsh 422