Xilinx 8.2i manual 11Simulation Points for HDL Designs

Chapter 2: Design Flow

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The following figure shows when you can perform functional and timing simulation:

HDL

Design

UniSim

Library

LogiBLOX

Modules

CORE Generator

Modules

SimPrim

Library

HDL RTL	Testbench
Simulation	Stimulus
Synthesis
Post-Synthesis Gate-Level
Functional Simulation
Xilinx
Implementation
HDL Timing
Simulation

X9243

Figure 2-11:Simulation Points for HDL Designs

The three primary simulation points can be expanded to allow for two post-synthesis simulations. These points can be used if the synthesis tool cannot write VHDL or Verilog, or if the netlist is not in terms of UniSim components. The following table lists all the simulation points available in the HDL design flow.

Table 2-2:Five Simulation Points in HDL Design Flow

Simulation	UniSim	SimPrim	SDF
RTL	X
Post-Synthesis	X
Functional Post-NGDBuild (Optional)		X
Functional Post-MAP (Optional)		X	X
Post-Route Timing		X	X

These simulation points are described in the “Simulation Points” section of the Synthesis and Simulation Design Guide.

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