Chapter 2: Design Flow

R

The following figure shows when you can perform functional and timing simulation:

HDL

Design

UniSim

Library

LogiBLOX

Modules

CORE Generator

Modules

SimPrim

Library

HDL RTL

Testbench

Simulation

Stimulus

Synthesis

 

Post-Synthesis Gate-Level

 

Functional Simulation

 

Xilinx

 

Implementation

 

HDL Timing

 

Simulation

 

X9243

Figure 2-11:Simulation Points for HDL Designs

The three primary simulation points can be expanded to allow for two post-synthesis simulations. These points can be used if the synthesis tool cannot write VHDL or Verilog, or if the netlist is not in terms of UniSim components. The following table lists all the simulation points available in the HDL design flow.

Table 2-2:Five Simulation Points in HDL Design Flow

Simulation

UniSim

SimPrim

SDF

 

 

 

 

RTL

X

 

 

 

 

 

 

Post-Synthesis

X

 

 

 

 

 

 

Functional Post-NGDBuild (Optional)

 

X

 

 

 

 

 

Functional Post-MAP (Optional)

 

X

X

 

 

 

 

Post-Route Timing

 

X

X

 

 

 

 

These simulation points are described in the “Simulation Points” section of the Synthesis and Simulation Design Guide.

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Xilinx 8.2i manual 11Simulation Points for HDL Designs, 2Five Simulation Points in HDL Design Flow UniSim SimPrim
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8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.
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