New new timing analysis | Xilinx 8.2i manual

Tcl Commands for General Usage

Table 3-5:Timing Analysis Properties and Descriptions

Analysis Property	Description

show_longest_paths	CPLD report option that determines whether
	the longest paths are shown.

show_delay_over	CPLD report option that specifies only paths
	above the specified delay are shown in the
	report.

show_delay_under	CPLD report option that specifies that only
	paths below the specified delay are shown in
	the report.

display_info	Specifies whether Timing Analyzer is run in
	verbose mode.

display_physical_name	Specifies whether physical names of path
	elements in the timing report should be
	displayed in the Timing Analyzer report view.

display_site_location	Specifies whether site locations of path
	elements in the timing report should be
	displayed in the Timing Analyzer report view.

display_statistics	Specifies whether the statistic section of the
	timing report is shown in the Timing Analyzer
	report view.

new (new timing analysis)

The timing_analysis new command sets up a new analysis or query on an implemented design in the current ISE project. The timing_analysis set command is used to set properties and values for the new analysis. See “set (set analysis properties)” for more information.

% timing_analysis new analysisquery [-name <analysis_name>]

timing_analysis is the name of the Xilinx Tcl command.

new is the name of the timing_analysis subcommand.

analysis, if specified, sets up a timing analysis.

query, if specified, sets up a net or timegroup analysis.

-name <analysis_name> specifies the name for the analysis. If the -namecommand is used, but no name is specified, an analysis is generated and has the name of the top-level module.

Example:	% timing_analysis new analysis [-name stopwatch_timing]

Description:	In this example, the timing_analysis new command is used to create a
	timing analysis named stopwatch_timing.

Tcl Return:

A new timing analysis.

Development System Reference Guide

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8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Xilinx 8.2i manual New new timing analysis

Models: 8.2i

new (new timing analysis)

Development System Reference Guide

8.2i specifications