Xilinx 8.2i manual Turns Engine PAR Multi-Tasking Option, Turns Engine Overview

Models: 8.2i

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Turns Engine (PAR Multi-Tasking Option)

Turns Engine (PAR Multi-Tasking Option)

This Xilinx Development System option allows you to use multiple systems (nodes) that are networked together for a multi-run PAR job, significantly reducing the total amount of time to completion. You can specify this multi-tasking option from the command line.

Turns Engine Overview

Before the Turns Engine was developed for the Xilinx Development System, PAR could only run multiple jobs in a linear way. The total time required to complete PAR was equal to the sum of the times that it took for each of the PAR jobs to run. This is illustrated by the following PAR command.

par –ol high n 10 mydesign.ncd output.dir

The preceding command tells PAR to run 10 place and route passes

(–n 10) at effort level high (–ol high). PAR runs each of the 10 jobs consecutively, generating an output NCD file for each job, (i.e., output.dir/high_high_1.ncd, output.dir/high_high_2.ncd, etc.). If each job takes approximately one hour, then the run takes approximately 10 hours.

The Turns Engine allows you to use multiple nodes at the same time, dramatically reducing the time required for all ten jobs. To do this you must first generate a file containing a list of the node names, one per line. The following example shows five nodes for running 10 jobs.

Note: A pound sign (#) in the example indicates a comment.

# NODE names

 

jupiter

#Fred’s node

mars

#Harry’s node

mercury

#Betty’s node

neptune

#Pam’s node

pluto

#Mickey’s node

Now run the job from the command line as follows:

par m nodefile_name –ol high n 10 mydesign.ncd output.dir

nodefile_name is the name of the node file you created.

This runs the following jobs on the nodes specified.

Table 9-6: Node Files

jupiter

par –ol high –i 10 –c 1 mydesign.ncd

 

output.dir/high_high_1.ncd

 

 

mars

par –ol high –i 10 –c 1 mydesign.ncd

 

output.dir/high_high_2.ncd

 

 

mercury

par –ol high –i 10 –c 1 mydesign.ncd

 

output.dir/high_high_3.ncd

 

 

neptune

par –ol high –i 10 –c 1 mydesign.ncd

 

output.dir/high_high_4.ncd

 

 

pluto

par –ol high –i 10 –c 1 mydesign.ncd

 

output.dir/high_high_5.ncd

 

 

Development System Reference Guide

www.xilinx.com

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Xilinx 8.2i manual Turns Engine PAR Multi-Tasking Option, Turns Engine Overview

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.