Xilinx 8.2i manual Offset in Detailed Path Data

R		OFFSET Constraints
Data Path Delay:	3.983ns	(Levels of Logic = 2)
Clock Path Delay:	-0.485ns (Levels of Logic = 3)
Clock Uncertainty:	0.000ns

Data Path: wr_enl to wr_addr[2]

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OFFSET IN Detailed Path Data

The first section is the data path. In the following case, the path starts at an IOB, goes through a look-up table (LUT) and is the clock enable pin of the destination flip-flop.

Example:

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Data Path: wr_enl to wr_addr[2]
Location	Delay type	Delay(ns) Logical Resource(s)
-------------------------------------------------			----------------
C4.I	Tiopi	0.825	wr_enl
			wr_enl_ibuf
SLICE_X2Y9.G3	net (fanout=39)	1.887	wr_enl_c
SLICE_X2Y9.Y	Tilo	0.439	G_82
SLICE_X3Y11.CE	net (fanout=1)	0.592	G_82
SLICE_X3Y11.CLK	Tceck	0.240	wr_addr[2]
-------------------------------------------------			---------------
Total	3.983ns (1.504ns logic, 2.479ns route)
		37.8% logic, 62.2% route)

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