Optimize Optimize Logic for Density or Speed

Chapter 18: CPLDfit

–optimize (Optimize Logic for Density or Speed)

-optimize densityspeed

This -optimize option directs CPLDfit to optimize the design for density or speed. Optimizing for density results in a slower speed but uses resource sharing to allow more logic to fit into a device. Optimizing for speed uses less resource sharing but flattens the logic, which results in fewer levels of logic (faster). Density is the default argument for this option.

–p (Specify Xilinx Part)

-ppart

The -p option specifies the Xilinx product family; <part> is in the form of device- speedgrade-package (for example, XC2C512-10-FT256).

If only a product family is entered (for example, XPLA3), CPLDfit iterates through all densities until a fit is found.

–pinfbk (Use Pin Feedback)

The XC9500 architecture allows feedback into the device through the I/O pin. The -pinfbk option turns this feedback functionality on. This option is on by default.

Architecture Support: XC9500

–power (Set Power Mode)

-power [stdlowauto]

The -power option sets the default power mode of macrocells. This option can be overridden if a macrocell is explicitly assigned a power setting. The std setting is for standard high speed mode. The low setting is for low power mode (at the expense of speed). The auto setting allows CPLDfit to choose the std or low setting based on the timing constraints. The default setting for this option is std.

Note: This option is available for XC9500/XL/XV devices.

–pterms (Number of Pterms to Use During Optimization)

-pterms [limit:1,90]

The -pterms option specifies the maximum number of product terms for a single equation. The higher this value, the more product term resources a single equation may use, possibly limiting the number of equations allowed in a single function block. The maximum limit varies with each CPLD architecture. The limits are as follows (default in parenthesis):

XC9500 = 90 (25)

XC9500XL/XV = 90 (25)

CoolRunner XPLA3 = 48 (36)

CoolRunner-II = 56 (36)

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Development System Reference Guide

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Xilinx 8.2i manual Optimize Optimize Logic for Density or Speed, Specify Xilinx Part

Models: 8.2i