Xilinx 1000BASE-X manual Virtex-4 Devices for Sgmii or Dynamic Standards Switching

RocketIO Logic with the Fabric Rx Elastic Buffer

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Virtex-4 Devices for SGMII or Dynamic Standards Switching

The core is designed to integrate with the Virtex-4 MGT. The connections and logic required between the core and MGT transceiver are illustrated in Figure 8-4–the signal names and logic in the figure precisely match those delivered with the example design when an MGT transceiver is used.

Note: A small logic shim (included in the “block” level wrapper) is required to convert between the port differences between the Virtex-II Pro and Virtex-4 MGTs. This is not illustrated in Figure 8-4.

The MGT clock distribution in Virtex-4 devices is column-based and consists of multiple MGT tiles (that contain two MGTs each). For this reason, the MGT transceiver wrapper delivered with the core always contains two MGT instantiations, even if only a single MGT is in use. Figure 8-4illustrates only a single MGT for clarity.

A GT11CLK_MGT primitive is also instantiated to derive the reference clocks required by the MGT column-based tiles. See the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide (UG076) for more information about layout and clock distribution.

The 250 MHz reference clock from the GT11CLK_MGT primitive is routed to the MGT, which is configured to internally synthesize a 125 MHz clock. This is output on the TXOUTCLK1 port of the MGT and once placed onto global clock routing, can be used by all core logic. This clock is input back into the MGT on the user interface clock port txusrclk2. With the attribute settings applied to the MGT from the example design, the txusrclk port is derived internally within the MGT using the internal clock dividers and does not need to be provided from the FPGA fabric.

It can be seen from Figure 8-4that the Rx Elastic Buffer is implemented in the FPGA fabric between the MGT and the core. This replaces the Rx Elastic Buffer in the MGT (which is bypassed).

This alternative Receiver Elastic Buffer uses a single block RAM to create a buffer twice as large as the one present in the MGT. It is able to cope with larger frame sizes before clock tolerances accumulate and result in emptying or filling of the buffer. This is necessary to guarantee SGMII operation at 10 Mbps where each frame size is effectively 100 times larger than the same frame would be at 1 Gbps because each byte is repeated 100 times (see “Designing with Client-side GMII for the SGMII Standard,” page 59).

In bypassing the MGT Rx Elastic Buffer, data is clocked out of the MGT synchronously to rxrecclk1. This clock can be placed on a BUFR component and is used to synchronize the transfer of data between the MGT and the Elastic Buffer, as illustrated in Figure 8-4. See also “Virtex-4 RocketIO MGTs for SGMII or Dynamic Standards Switching Constraints,” page 166.

The MGT transceivers require a calibration block to be included in the fabric logic. The example design provided with the core instantiates calibration blocks as required. Calibration blocks require a clock source of between 25 to 50 MHz, which is shared with the Dynamic Reconfiguration Port (DRP) of the MGT, named dclk in the example design. See Xilinx Answer Record 22477 for more information.

Figure 8-4also illustrates the TX_SIGNAL_DETECT and RX_SIGNAL_DETECT ports of the calibration block, which should be driven to indicate whether or not dynamic data is being transmitted and received through the MGT (see Virtex-4 Errata). However, RX_SIGNAL_DETECT is connected to the signal_detect port of the example design. signal_detect is intended to indicate to the core that valid data is being received. When not asserted, the calibration block will switch the MGT into loopback to force dynamic data through the MGT receiver path.

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UG155 March 24, 2008