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RocketIO Transceiver Logic
R
Virtex-5 FXT Devices
The core is designed to integrate with the
Note: A small logic shim (included in the
A GTX tile consists of a pair of transceivers. For this reason, the GTX transceiver wrapper delivered with the core always contains two GTX instantiations, even if only a single GTX transceiver tile is in use. Figure
The 125 MHz differential reference clock is routed directly to the GTX transceiver. The GTX transceiver is configured to output a version of this clock on the REFCLKOUT port: this is then routed to a DCM.
From the DCM, the CLK0 port (125MHz) is placed onto global clock routing and can be used as the 125MHz clock source for all core logic: this clock is also input back into the GTX transceiver on the user interface clock ports rxusrclk2 and txusrclk2.
From the DCM, the CLKDV port (62.5MHz) is placed onto global clock routing and is input back into the GTX transceiver on the user interface clock ports rxusrclk and txusrclk.
See also
Virtex-5 RocketIO GTX Wizard
The two wrapper files immediately around the GTX transceiver pair,
rocketio_wrapper_gtx_tile and rocketio_wrapper_gtx (see Figure
The CORE Generator log file (XCO file) which was created when the RocketIO GTX Wizard project was generated is available in the following location:
<project_directory>/<component_name>/example_design/transceiver/ rocketio_wrapper_gtx.xco
This file can be used as an input to the CORE Generator to regenerate the RocketIO wrapper files. The XCO file itself contains a list of all of the GTX Wizard attributes which were used. For further information, please refer to the
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