Xilinx 1000BASE-X manual Mdio Management Interface Pinout Optional, Mac

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Chapter 2: Core Architecture

MDIO Management Interface Pinout (Optional)

Table 2-3describes the optional MDIO interface signals of the core used to access the PCS Management Registers. These signals are typically connected to the MDIO port of a MAC device, either off-chip or to an internally integrated MAC core. For more information, see “Management Registers” in Chapter 9.

Table 2-3:Optional MDIO Interface Signal Pinout

Signal	Direction	Clock	Description
		Domain
mdc	Input	N/A	Management clock (<= 2.5 MHz).
mdio__in1	Input	mdc	Input data signal for communication with
			MDIO controller (for example, an Ethernet
			MAC). Tie high if unused.
mdio_out1	Output	mdc	Output data signal for communication with
			MDIO controller (for example, an Ethernet
			MAC).
mdio_tri1	Output	mdc	Tri-state control for MDIO signals; ‘0’ signals
			that the value on mdio_out should be asserted
			onto the MDIO interface.
phyad[4:0]	Input	N/A	Physical Address of the PCS Management
			register set. It is expected that this signal will be
			tied off to a logical value.

1.These signals can be connected to a Tri-state buffer to create a bidirectional mdio signal suitable for connection to an external MDIO controller (for example, an Ethernet MAC).

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		UG155 March 24, 2008