R

Appendix E: Rx Elastic Buffer Specifications

Virtex-II Pro/Virtex-5

 

Virtex-4 FX

RocketIO Transceiver

 

RocketIO Transceiver

Rx Elastic Buffer

 

Rx Elastic Buffer

 

 

 

52 - Overflow Mark

57 - Overflow Mark

CLK_COR_MAX_LAT + 2

64

34

30

64

CLK_COR_MIN_LAT - 2

16 - Underflow Mark

12 - Underflow Mark

Figure E-1:Elastic Buffer Sizes for all RocketIO Transceiver Families

Virtex-II Pro and Virtex-5 Devices

Consider the Virtex-II Pro and Virtex-5 FPGA example, where the shaded area represents the usable buffer availability for the duration of frame reception.

If the buffer is filling during frame reception, there are 52-34 = 18 FIFO locations available before the buffer reaches the overflow mark.

If the buffer is emptying during reception, then there are 30-12 = 18 FIFO locations available before the buffer reaches the underflow mark.

This analysis assumes that the buffer is approximately at the half-full level at the start of the frame reception. As illustrated, there are two locations of uncertainty, above and below the exact half-full mark of 32, resulting from the clock correction decision, and is based across an asynchronous boundary.

Because there is a worst-case scenario of one clock edge difference every 5000 clock periods, the maximum number of clock cycles (bytes) that can exist in a single frame passing through the buffer before an error occurs is:

5000 x 18 = 90000 bytes

Table E-1translates this into maximum frame size at different Ethernet speeds. At SGMII speeds lower than 1 Gbps, performance is diminished because bytes are repeated multiple times (see “Designing with Client-side GMII for the SGMII Standard” in Chapter 5).

Table E-1:Maximum Frame Sizes: RocketIO Transceiver Rx Elastic Buffers (100ppm Clock Tolerance)

Standard / Speed

Maximum Frame Size

1000BASE-X (1 Gbps only)

90000

SGMII (1 Gbps)

90000

SGMII (100 Mbps)

9000

SGMII (10 Mbps)

900

220

www.xilinx.com

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

 

 

UG155 March 24, 2008

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Xilinx 1000BASE-X manual Virtex-II Pro and Virtex-5 Devices, Appendix E Rx Elastic Buffer Specifications