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Xilinx 1000BASE-X Register 5: SGMII Auto-Negotiation Link Partner Ability

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140 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

UG155 March 24, 2008

Chapter 9: Configuration and Status

R

Register 5: SGMII Auto-Negotiation Link Partner Ability

The Auto-Negotiation Ability Base Register (Register 5) contains information related to the

status of the link between the PHY and its physical link partner across the Medium.

MDIO Register 5: SGMII Auto-Negotiation Link Partner Ability

Table 9-23: SGMII Auto-Negotiation Link Partner Ability Base (Register 5)

Bit(s) Name Description Attributes Default

Value

5.15 PHY Link

Status

This refers to the link status of the PHY with its

link partner across the Medium.

1 = Link Up

0 = Link Down

read only 1

5.14 Acknowle

dge

Used by Auto-Negotiation function to indicate

reception of a link partner’s base or next page

read only 0

5.13 Reserved Always returns ‘0,’ writes ignored returns 0 0

5.12 Duplex

Mode

1= Full Duplex

0 = Half Duplex

read only 0

5.11:10 Speed 11 = Reserved

10 = 1 Gbps

01 = 100 Mbps

00 = 10 Mbps

read only 00

5.9:1 Reserved Always return 0s returns 0s 000000000

5:0 Reserved Always returns ‘1’ returns 1 1

PHY LINK STATUS

ACKNOWLEDGE

RESERVED

RESERVED

15 14 13 12 11 0

Reg 5

DUPLEX MODE

91

10

SPEED

RESERVED

Contents

Main UG155 March 24, 2008 Revision History The following table shows the revision history for this document. Date Doc Versio n Revision Table of Contents Schedule of Figures Schedule of Tables Preface: About This Guide Chapter 1: Introduction Chapter 3: Generating and Customizing the Core Chapter 5: Using the Client-side GMII Data Path Chapter 6: The Ten-Bit Interface Chapter 7: 1000BASE-X with RocketIO Transceivers Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers MDIO Management Interface Chapter 10: Auto-Negotiation Overview of Operation Setting the Configurable Link Timer Using the Auto-Negotiation Interrupt Chapter 11: Dynamic Switching of 1000BASE-X and SGMII Standards Chapter 13: Interfacing to Other Cores Chapter 14: Special Design Considerations Chapter 15: Implementing the Design Appendix A: Core Verification, Compliance, and Interoperability Appendix B: Core Latency Appendix C: Calculating the DCM Fixed Phase Shift Value Appendix F: Debugging Guide Page Schedule of Figures Chapter 3: Generating and Customizing the Core Chapter 5: Using the Client-side GMII Data Path Chapter 6: The Ten-Bit Interface Chapter 7: 1000BASE-X with RocketIO Transceivers Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers Chapter 10: Auto-Negotiation Chapter 11: Dynamic Switching of 1000BASE-X and SGMII Standards Chapter 13: Interfacing to Other Cores Chapter 14: Special Design Considerations Page Schedule of Tables Chapter 3: Generating and Customizing the Core Page Preface About This Guide Guide Contents Conventions Typographical design_name Online Document option_name design_name block_name loc1 loc2 ... locn; Page Chapter 1 Introduction About the Core Designs Using RocketIO Transceivers Recommended Design Experience Additional Core Resources Related Xilinx Ethernet Products and Services Specifications Technical Support Feedback Document Page Chapter 2 Core Architecture System Overview Ethernet 1000BASE-X PCS/PMA or SGMII Using A RocketIO Transceiver GMII Block PCS Transmit Engine PCS Receive Engine and Synchronization Optional Auto-Negotiation Block Optional PCS Management Registers Ethernet 1000BASE-X PCS/PMA or SGMII with Ten-Bit-Interface 8B/10B Encoder 8B/10B Decoder Receiver Elastic Buffer TBI Block Core Interfaces Core Interfaces functionality. For more information, see Chapter 3, Generating and Customizing the Core. Figure 2-3: Component Pinout Using RocketIO Transceiver with PCS Management Registers Chapter 2: Core Architecture Figure 2-4: Component Pinout Using RocketIO Transceiver without PCS Management Registers Page Chapter 2: Core Architecture Figure 2-6: Component Pinout Using Ten-Bit Interface without PCS Management Registers Client Side Interface GMII Pinout Page Core Interfaces Common Signal Pinout MDIO Management Interface Pinout (Optional) Configuration Vector (Optional) Auto-Negotiation Signal Pinout Dynamic Switching Signal Pinout Physical Side Interface 1000BASE-X PCS with PMA Using RocketIO Transceiver Signal Pinout (Optional) Page 1000BASE-X PCS with TBI Pinout Chapter 3 Generating and Customizing the Core GUI Interface Component Name Select Standard Core Functionality Physical Interface MDIO Management Interface Auto-Negotiation SGMII/Dynamic Standard Switching Elastic Buffer Options Page RocketIO Tile Configuration Parameter Values in the XCO File Output Generation Chapter 4 Designing with the Core Design Overview 1000BASE-X Standard Using RocketIO Transceiver Example Design 1000BASE-X Standard with TBI Example Design SGMII Standard Using a RocketIO Transceiver Example Design SGMII Standard with TBI Transceiver Example Design Design Guidelines Generate the Core Examine the Example Design Provided with the Core Implement the Ethernet 1000BASE-X PCS/PMA or SGMII Core in Your Application Write an HDL Application Synthesize your Design Create a Bitstream Simulate and Download your Design Know the Degree of Difficulty Keep it Registered Recognize Timing Critical Signals Use Supported Design Flows Make Only Allowed Modifications Chapter 5 Using the Client-side GMII Data Path Designing with the Client-side GMII for the 1000BASE-X Standard GMII Transmission Normal Frame Transmission Error Propagation GMII Reception Normal Frame Reception Normal Frame Reception with Extension Field Frame Reception with Errors False Carrier status_vector[4:0] signals Bit[0]: Link Status Bit[1]: Link Synchronization Bits[4:2]: Code Group Reception Indicators Bit[2]: RUDI(/C/) Using the Virtex-II Pro RocketIO Transceiver CRC Functionality GMII Transmission GMII Reception Designing with Client-side GMII for the SGMII Standard Overview GMII Transmission 1 Gigabit per Second Frame Transmission 100 Megabit per Second Frame Transmission GMII Reception 1 Gigabit per Second Frame Reception 100 Megabit per Second Frame Reception 10 Megabit per Second Frame Reception Using the GMII as an Internal Connection Implementing External GMII GMII Transmitter Logic Chapter 5: U sing the Client-side GMII Data Path Virtex-II Pro and Virtex-II Devices Figure 5-14: GMII Transmitter Logic Spartan-3, Spartan-3E and Spartan-3A Devices Page Virtex-5 Devices GMII Receiver Logic Implementing External GMII Figure 5-18: External GMII Receiver Logic Page Chapter 6 The Ten-Bit Interface Ten-Bit-Interface Logic Transmitter Logic Receiver Logic Virtex-II and Virtex-II Pro Devices Ten-Bit-Interface Logic component_name Figure 6-2: Ten-Bit-Interface Receiver Logic _block (Block Level from example design) Spartan-3, Spartan-3E and Spartan-3A Devices Method 1 Chapter 6: The Ten-Bit Interface Method 2 Figure 6-5: Alternate Ten-Bit Interface Receiver Logic for Virtex-4 Devices Virtex-5 Devices Method 1 Method 2 Clock Sharing across Multiple Cores with TBI Page Chapter 7 1000BASE-X with RocketIO Transceivers RocketIO Transceiver Logic Figure 7-1: 1000BASE-X Connection to a Virtex-II Pro MGT component_name_block (Block Level from example design) Page Figure 7-2: 1000BASE-X Connection to Virtex-4 MGT '0' '0' '1' component_name_block (Block Level from example design) Virtex-5 RocketIO GTP Wizard Figure 7-3: 1000BASE-X Connection to Virtex-5 GTP Transceivers component_name_block (Block Level from example design) rocketio_wrapper_gtp_tile clkin (125MHz) rocketio_wrapper_gtp Virtex-5 RocketIO GTX Wizard Figure 7-4: 1000BASE-X Connection to Virtex-5 GTX Transceivers userclk2 (125MHz) DCM CLKIN CLK0 FB CLKDV userclk (62.5MHz) Clock Sharing Across Multiple Cores with RocketIO Page Figure 7-6: Clock Management - Multiple Core Instances, MGTs for 1000BASE-X Page Page Page DCM CLKIN CLK0 FB BUFG CLKDV BUFG Page Chapter 8 SGMII / Dynamic Standards Switching with RocketIO Transceivers Receiver Elastic Buffer Implementations Selecting the Buffer Implementation from the GUI The Requirement for the FPGA Fabric Rx Elastic Buffer Analysis FPGA The RocketIO Rx Elastic Buffer Closely Related Clock Sources Case 1 Case 2 RocketIO Logic using the RocketIO Rx Elastic Buffer FPGA RocketIO Logic with the Fabric Rx Elastic Buffer Figure 8-3: SGMII Connection to a Virtex-II Pro RocketIO Transceiver 100 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 FPGA fabric Rx Elastic Buffer local clock routing component_name_block (Block Level from example design) Virtex-4 Devices for SGMII or Dynamic Standards Switching 102 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 Caution! '1' '0' Figure 8-4: SGMII Connection to a Virtex-4 MGT Virtex-5 LXT or SXT Devices for SGMII or Dynamic Standards Switching Virtex-5 RocketIO GTP Wizard . Figure 8-5: SGMII Connection to a Virtex-5 RocketIO GTP Transceiver Virtex-5 FXT Devices for SGMII or Dynamic Standards Switching Virtex-5 RocketIO GTX Wizard Figure 8-6: SGMII Connection to a Virtex-5 RocketIO GTX Transceiver userclk2 (125MHz) DCM CLKIN CLK0 FB CLKDV userclk (62.5MHz) Clock Sharing - Multiple Cores with RocketIO, Fabric Elastic Buffer component_name Figure 8-7: Clock Management with Multiple Core Instances with Virtex-II Pro local clock routing Page Figure 8-8: Clock Management with Multiple Core Instances with Virtex-4 MGTs for SGMII component_name_block (Block Level) Page Figure 8-9: Clock Management with Multiple Core Instances with Virtex-5 GTP component_name_block (Block Level) Page Figure 8-10: Clock Management with Multiple Core Instances with Virtex-5 GTX component_name_block (Block Level) DCM CLKIN CLK0 FB BUFG CLKDV BUFG Configuration and Status MDIO Management Interface MDIO Bus System MDIO Transactions PHY1 (MMD) PHY2 (MMD) MAC (STA) Write Transaction MDIO Addressing Physical Address (PHYAD) Register Address (REGAD) Connecting the MDIO to an Internally Integrated STA Connecting the MDIO to an External STA Management Registers 1000BASE-X Standard Using the Optional Auto-Negotiation Register 0: Control Register Table 9-2: MDIO Registers for 1000BASE-X with Auto-Negotiation (Continued) MDIO Register 0: Control Register Table 9-3: Control Register (Register 0) Table 9-3: Control Register (Register 0) (Continued) Register 1: Status Register MDIO Register 1: Status Register Table 9-4: Status Register (Register 1) Registers 2 and 3: PHY Identifiers Table 9-4: Status Register (Register 1) (Continued) Registers 2 and 3: PHY Identifiers Register 4: Auto-Negotiation Advertisement Table 9-5: PHY Identifier (Registers 2 and 3) MDIO Register 4: Auto-Negotiation Advertisement Table 9-6: Auto-Negotiation Advertisement Register (Register 4) Register 5: Auto-Negotiation Link Partner Base Table 9-6: Auto-Negotiation Advertisement Register (Register 4) (Continued) MDIO Register 5: Auto-Negotiation Link Partner Base Table 9-7: Auto-Negotiation Link Partner Ability Base Register (Register 5) Register 6: Auto-Negotiation Expansion Register 7: Next Page Transmit Table 9-7: Auto-Negotiation Link Partner Ability Base Register (Register 5) MDIO Register 6: Auto-Negotiation Expansion Table 9-8: Auto-Negotiation Expansion Register (Register 6) Register 8: Next Page Receive Table 9-9: Auto-Negotiation Next Page Transmit (Register 7) MDIO Register 8: Next Page Receive Table 9-10: Auto-Negotiation Next Page Receive (Register 8) Register 15: Extended Status Table 9-10: Auto-Negotiation Next Page Receive (Register 8) (Continued) MDIO Register 15: Extended Status Register Table 9-11: Extended Status Register (Register 15) Register 16: Vendor-Specific Auto-Negotiation Interrupt Control 1000BASE-X Standard Without the Optional Auto-Negotiation MDIO Register 16: Vendor Specific Auto-Negotiation Interrupt Control Table 9-12: Vendor Specific Register: Auto-Negotiation Interrupt Control Register (Register 16) Table 9-13: MDIO Registers for 1000BASE-X without Auto-Negotiation Register 0: Control Register MDIO Register 0: Control Register Table 9-14: Control Register (Register 0) Register 1: Status Register Table 9-14: Control Register (Register 0) (Continued) MDIO Register 1: Status Register Table 9-15: Status Register (Register 1) Table 9-15: Status Register (Register 1) (Continued) Registers 2 and 3: Phy Identifier Register 15: Extended Status Table 9-16: PHY Identifier (Registers 2 and 3) MDIO Register 15: Extended Status Table 9-17: Extended Status (Register 15) SGMII Standard Using the Optional Auto-Negotiation Register 0: SGMII Control Table 9-19: SGMII Control (Register 0) Register 1: SGMII Status Table 9-19: SGMII Control (Register 0) (Continued) MDIO Register 1: SGMII Status Table 9-20: SGMII Status (Register 1) Table 9-20: SGMII Status (Register 1) (Continued) Registers 2 and 3: PHY Identifier Register 4: SGMII Auto-Negotiation Advertisement Table 9-21: PHY Identifier (Registers 2 and 3) MDIO Register 4: SGMII Auto-Negotiation Advertisement Table 9-22: SGMII Auto-Negotiation Advertisement (Register 4) Register 5: SGMII Auto-Negotiation Link Partner Ability MDIO Register 5: SGMII Auto-Negotiation Link Partner Ability Register 6: SGMII Auto-Negotiation Expansion Register 7: SGMII Auto-Negotiation Next Page Transmit MDIO Register 6: SGMII Auto-Negotiation Expansion Table 9-24: SGMII Auto-Negotiation Expansion (Register 6) MDIO Register 7: SGMII Auto-Negotiation Next Page Transmit Register 8: SGMII Next Page Receive Table 9-25: SGMII Auto-Negotiation Next Page Transmit (Register 7) MDIO Register 8: SGMII Next Page Receive Table 9-26: SGMII Auto-Negotiation Next Page Receive (Register 8) Register 15: SGMII Extended Status MDIO Register 15: SGMII Extended Status Table 9-27: SGMII Extended Status Register (Register 15) Register 16: SGMII Auto-Negotiation Interrupt Control MDIO Register 16: SGMII Auto-Negotiation Interrupt Control Table 9-28: SGMII Auto-Negotiation Interrupt Control (Register 16) SGMII Standard without the Optional Auto-Negotiation Register 0: SGMII Control Table 9-30: SGMII Control (Register 0) Register 1: SGMII Status Table 9-30: SGMII Control (Register 0) (Continued) MDIO Register 1: SGMII Status Table 9-31: SGMII Status (Register 1) Table 9-31: SGMII Status (Register 1) (Continued) Registers 2 and 3: PHY Identifier Register 4: SGMII Auto-Negotiation Advertisement Table 9-32: PHY Identifier (Registers 2 and 3) MDIO Register 4: SGMII Auto-Negotiation Advertisement Table 9-33: SGMII Auto-Negotiation Advertisement (Register 4) Both 1000BASE-X and SGMII Standards Register 17: Vendor-specific Standard Selection Register Optional Configuration Vector Page Chapter 10 Auto-Negotiation Overview of Operation 1000BASE-X Standard Page SGMII Standard Setting the Configurable Link Timer 1000BASE-X Standard SGMII Standard Simulating Auto-Negotiation Using the Auto-Negotiation Interrupt Dynamic Switching of 1000BASE-X and SGMII Standards Typical Application Operation of the Core Selecting the Power-On / Reset Standard Switching the Standard Using MDIO Auto-Negotiation State Machine Setting the Auto-Negotiation Link Timer Page Page Chapter 12 Constraining the Core Required Constraints Device, Package, and Speedgrade Selection I/O Location Constraints Placement Constraints Setting MGT Attributes MGT Transceiver Placement Constraints Virtex-II Pro RocketIO MGTs for SGMII or Dynamic Standards Switching Constraints Virtex-4 RocketIO MGTs for 1000BASE-X Constraints Setting MGT Transceiver Attributes MGT Placement Constraints Virtex-4 RocketIO MGTs for SGMII or Dynamic Standards Switching Constraints Virtex-5 RocketIO GTP Transceivers for 1000BASE-X Constraints Setting GTP Transceiver Attributes Virtex-5 RocketIO GTP Transceivers for SGMII or Dynamic Standards Switching Constraints Setting GTP Transceiver Attributes Virtex-5 RocketIO GTX Transceivers for 1000BASE-X Constraints Setting GTX Transceiver Attributes Virtex-5 RocketIO GTX Transceivers for SGMII or Dynamic Standards Switching Constraints Setting GTX Transceiver Attributes Ten-Bit Interface Constraints Ten-Bit Interface IOB Constraints TBI Input Setup/Hold Timing Input TBI Timing Specification t SETUP t Virtex-II, and Virtex-II Pro Devices Spartan-3, Spartan-3E, and Spartan-3A Devices Virtex-4 Devices Virtex-5 Devices Constraints When Implementing an External GMII GMII IOB Constraints GMII Input Setup/Hold Timing Input GMII timing specification Virtex-II, and Virtex-II Pro devices Spartan-3, Spartan-3E, and Spartan-3A devices Virtex-4 devices Virtex-5 devices Understanding Timing Reports for Setup/Hold Timing Devices Other Than Virtex-4 or Virtex-5 Virtex-4 or Virtex-5 Devices = 8 - 6.501 = 1.499 ns = 7.893 - 8 = -0.107 ns Page Chapter 13 Interfacing to Other Cores Integrating with the 1-Gigabit Ethernet MAC Core Integration of the 1-Gigabit Ethernet MAC to 1000BASE-X PCS with TBI Page Integrating with the 1-Gigabit Ethernet MAC Core Integration of the 1-Gigabit Ethernet MAC Using a RocketIO Transceiver Virtex-II Pro Devices Chapter 13: Interfacing to Other Cores Figure 13-3: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA Using a Virtex-4 MGT 1-Gigabit Ethernet MAC LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE Virtex-4 GT11 RocketIO Virtex-5 LXT and SXT Devices Virtex-5 FXT Devices Integration of the 1-Gigabit Ethernet MAC to Provide SGMII (or Dynamic Switching) Functionality Integrating with the Tri-Mode Ethernet MAC Core Page Figure 13-6: Tri-Speed Ethernet MAC Extended to use an SGMII with TBI IOB LOGIC Virtex-II Pro Devices Figure 13-7: Tri-Speed Ethernet MAC Extended to use an SGMII in Virtex-II Pro Page Figure 13-8: Tri-Speed Ethernet MAC Extended to Use an SGMII in Virtex-4 Virtex-5 LXT and SXT Devices Figure 13-9: Tri-Speed Ethernet MAC Extended to use an SGMII in Virtex-5 LXT/SXT Virtex-5 FXT Devices Figure 13-10: Tri-Speed Ethernet MAC Extended to use an SGMII in Virtex-5 FXT DCM CLKIN CLK0 FB BUFG BUFG CLKDV Page Chapter 14 Special Design Considerations Power Management Startup Sequencing Loopback Core with the TBI Core with RocketIO Transceiver Page Page Chapter 15 Implementing the Design component_name Pre-implementation Simulation Using the Simulation Model Synthesis Implementation Generating the Xilinx Netlist Mapping the Design Placing and Routing the Design Static Timing Analysis Post-Implementation Simulation Generating a Simulation Model Using the Model Virtex-5 Devices Virtex-4 and Virtex-II Pro Devices Other Implementation Information Appendix A Core Verification, Compliance, and Interoperability Verification Simulation Hardware Verification Page Appendix B Core Latency Core Latency Latency for 1000BASE-X PCS with TBI Transmit Path Latency Receive Path Latency Latency for 1000BASE-X PCS and PMA Using a RocketIO Transceiver Transmit Path Latency Receive Path Latency Latency for SGMII Appendix C Calculating the DCM Fixed Phase Shift Value Requirement for DCM Phase Shifting Finding the Ideal Phase Shift Value for Your System Page Appendix D 1000BASE-X State Machines Introduction Start of Frame Encoding The Even Transmission Case Reception of the Even Case The Odd Transmission Case Reception of the Odd Case Preamble Shrinkage End of Frame Encoding The Even Transmission case Reception of the Even Case The Odd Transmission Case Reception of the Odd Case Page Appendix E Rx Elastic Buffer Specifications Introduction Rx Elastic Buffers: Depths and Maximum Frame Sizes RocketIO Rx Elastic Buffers Virtex-II Pro and Virtex-5 Devices 64 64 Virtex-4 FX SGMII Fabric Rx Elastic Buffer 12 8 SGMII FPGA Fabric Rx Elastic Buffer TBI Rx Elastic Buffer For SGMII / Dynamic Switching 3218 For 1000BASE-X TBI Rx Elastic Buffer Clock Correction Idle Character Removal at 1Gbps (1000BASE-X and SGMII) Idle Character Removal at 100 Mbps (SGMII) Idle Character Removal at 10 Mbps (SGMII) Maximum Frame Sizes for Sustained Frame Reception Jumbo Frame Reception Appendix F Debugging Guide General Checks Problems with the MDIO Problems with Data Reception or Transmission Problems with Auto-Negotiation Problems in Obtaining a Link (Auto-Negotiation Disabled) RocketIO Transceiver Specific Problems with a High Bit Error Rate Symptoms Debugging RocketIO Transceiver Specific Checks