R

Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers

IOB LOGIC

brefclkp IBUFGDS

IPAD

brefclk (62.5MHz)

IPAD brefclkn

DCM

CLKIN CLK0 FB

CLK2X180

LOCKED

BUFG

BUFG

userclk (62.5MHz)

userclk2 (125MHz)

component_name_block

 

Virtex-II Pro

(Block Level from

RocketIO

example design)

(GT_CUSTOM)

 

 

 

REFCLKSEL

Ethernet 1000BASE-X

 

NC

REFCLK

PCS/PMA or SGMII

GND

REFCLK2

LogiCORE

 

NC

 

 

 

BREFCLK

userclk

 

NC

BREFCLK2

userclk2

 

 

TXUSRCLK

dcm_locked

 

 

TXUSRCLK2

 

 

 

 

 

GND

LOOPBACK[1:0]

powerdown

 

 

POWERDOWN

txchardispmode

 

 

TXCHARDISPMODE

txchardispval

 

 

TXCHARDISPVAL

txcharisk

 

 

TXCHARISK

txdata[7:0]

 

 

TXDATA[7:0]

mgt_rx_reset

 

 

RXRESET

mgt_tx_reset

 

 

TXRESET

rxbufstatus[1:0]

FPGA

 

 

rxchariscomma

 

RXCHARISCOMMA[1:0]

fabric

 

rxcharisk

 

RXCHARISK[1:0]

Rx

 

 

 

 

rxclkcorcnt[2:0]

Elastic

 

 

rxdata[7:0]

Buffer

 

RXDATA[15:0]

rxdisperr

 

 

RXDISPERR[1:0]

 

 

 

 

 

 

RXUSRCLK

 

 

 

RXUSRCLK2

enablealign

D

Q

ENPCOMMAALIGN

ENMCOMMAALIGN

 

 

 

 

local

 

RXRECCLK

 

 

RXPOLARITY

 

clock

 

 

 

TXPOLARITY

 

routing

 

 

 

 

TXFORCECRCERR

 

 

 

TXINHIBIT

 

 

GND

 

Figure 8-3:SGMII Connection to a Virtex-II Pro RocketIO Transceiver

100

www.xilinx.com

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

 

 

UG155 March 24, 2008

Page 100
Image 100
Xilinx 1000BASE-X manual 3SGMII Connection to a Virtex-II Pro RocketIO Transceiver