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Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers
IOB LOGIC
brefclkp IBUFGDS
IPAD | brefclk (62.5MHz) |
IPAD brefclkn
DCM
CLKIN CLK0 FB
CLK2X180
LOCKED
BUFG
BUFG
userclk (62.5MHz)
userclk2 (125MHz)
component_name_block |
| |
(Block Level from | ||
RocketIO | ||
example design) | ||
(GT_CUSTOM) |
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|
| REFCLKSEL | |
Ethernet |
| NC | REFCLK | |
PCS/PMA or SGMII | GND | REFCLK2 | ||
LogiCORE |
| NC | ||
|
|
| BREFCLK | |
userclk |
| NC | BREFCLK2 | |
userclk2 |
|
| TXUSRCLK | |
dcm_locked |
|
| TXUSRCLK2 | |
|
|
| ||
|
| GND | LOOPBACK[1:0] | |
powerdown |
|
| POWERDOWN | |
txchardispmode |
|
| TXCHARDISPMODE | |
txchardispval |
|
| TXCHARDISPVAL | |
txcharisk |
|
| TXCHARISK | |
txdata[7:0] |
|
| TXDATA[7:0] | |
mgt_rx_reset |
|
| RXRESET | |
mgt_tx_reset |
|
| TXRESET | |
rxbufstatus[1:0] | FPGA |
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| |
rxchariscomma |
| RXCHARISCOMMA[1:0] | ||
fabric |
| |||
rxcharisk |
| RXCHARISK[1:0] | ||
Rx |
| |||
|
|
| ||
rxclkcorcnt[2:0] | Elastic |
|
| |
rxdata[7:0] | Buffer |
| RXDATA[15:0] | |
rxdisperr |
|
| RXDISPERR[1:0] | |
|
|
| ||
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|
| RXUSRCLK | |
|
|
| RXUSRCLK2 | |
enablealign | D | Q | ENPCOMMAALIGN | |
ENMCOMMAALIGN | ||||
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| ||
| local |
| RXRECCLK | |
|
| RXPOLARITY | ||
| clock |
| ||
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| TXPOLARITY | ||
| routing |
| ||
|
|
| TXFORCECRCERR | |
|
|
| TXINHIBIT | |
|
| GND |
|
Figure 8-3: SGMII Connection to a Virtex-II Pro RocketIO Transceiver
100 | www.xilinx.com | Ethernet |
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| UG155 March 24, 2008 |