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Xilinx 1000BASE-X manual Clock Sharing Across Multiple Cores with RocketIO

Models: 1000BASE-X

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Clock Sharing Across Multiple Cores with RocketIO

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Clock Sharing Across Multiple Cores with RocketIO

Virtex-II Pro Devices

Figure 7-5illustrates sharing clock resources across two instantiations of the core on the same half of the device when using the core with the Virtex-II Pro MGT. Note that more can be added by instantiating the cores using the block level (from the example design) and continuing to share userclk, userclk2, and brefclk across all instantiations. For each core, userclk and userclk2 must always be derived from the brefclk or refclk used by that core.

When using the fixed routing resources of brefclk, MGTs along the top edge of the device must use a separate brefclk routing resource to those along the bottom edge of the device. For more information, see the Virtex-II Pro RocketIO Transceiver User Guide (UG024). Each brefclk domain must use its own DCM to derive its version of userclk and userclk2.

Customer Design

brefclkp IBUFGDS IPAD

IPAD brefclkn

		brefclk (62.5MHz)

DCM		BUFG
CLKIN	CLK0	userclk (62.5 MHz)
CLKIN	CLK0
FB CLK2X180		userclk2 (125 MHz)
FB CLK2X180
		BUFG

component_name_block (Block Level)

	Ethernet 1000BASE-X		GT_ETHERNET_1
	PCS/PMA or
	SGMII core		BREFCLK
	userclk		TXUSRCLK
	userclk		TXUSRCLK
	userclk2		TXUSRCLK2
			RXUSRCLK
			RXUSRCLK2


component_name_block
(Block Level)

Ethernet 1000BASE-X

PCS/PMA or

SGMII core

userclk userclk2

GT_ETHERNET_1

BREFCLK

TXUSRCLK

TXUSRCLK2

RXUSRCLK

RXUSRCLK2

Figure 7-5:Clock Management: Two Core Instances, Virtex-II Pro

MGTs for 1000BASE-X

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

www.xilinx.com

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UG155 March 24, 2008

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Xilinx 1000BASE-X manual Clock Sharing Across Multiple Cores with RocketIO

Contents

UG155 March 24 LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SgmiiDate Doc Revision Version Revision HistoryTable of Contents Using the Client-side Gmii Data Path Configuration and Status Interfacing to Other Cores Appendix C Calculating the DCM Fixed Phase Shift Value UG155 March 24 Schedule of Figures 1Functional Block Diagram Using RocketIO TransceiverAuto-Negotiation Typical Application for Dynamic Switching 157 UG155 March 24 Schedule of Tables 5Optional Auto-Negotiation Interface Signal Pinout33SGMII Auto-Negotiation Advertisement Register 4 About This Guide Guide ContentsConvention Meaning or Use Example ConventionsTypographical Preface About This GuideConventions Meaning or Use Example Online DocumentPreface About This Guide Recommended Design Experience Designs Using RocketIO TransceiversIntroduction About the CoreEthernet 1000BASE-X PCS/PMA or Sgmii Core Additional Core ResourcesTechnical Support FeedbackFeedback DocumentIntroduction System Overview Core ArchitectureOptional Auto-Negotiation Block Gmii BlockPCS Transmit Engine PCS Receive Engine and SynchronizationSystem Overview Ethernet 1000BASE-X PCS/PMA or Sgmii with Ten-Bit-InterfaceOptional PCS Management Registers RocketIO Interface BlockReceiver Elastic Buffer Core Interfaces8B/10B Encoder 8B/10B DecoderCore Interfaces Core Architecture Core Interfaces Core Architecture Gmii Pinout Client Side InterfaceEthernet 1000BASE-X PCS/PMA or Sgmii 2Other Common Signals Direction Description Common Signal PinoutMAC Mdio Management Interface Pinout OptionalConfiguration Vector Optional Auto-Negotiation Signal Pinout5Optional Auto-Negotiation Interface Signal Pinout Physical Side Interface Dynamic Switching Signal PinoutEthernet 1000BASE-X PCS/PMA or Sgmii 1000BASE-X PCS with TBI Pinout Generating and Customizing the Core GUI InterfaceComponent Name Select Standard Core FunctionalityGenerating and Customizing the Core Auto-Negotiation SGMII/Dynamic Standard Switching Elastic Buffer OptionsPhysical Interface Mdio Management Interface3SGMII/Dynamic Standard Switching Options Screen RocketIO Tile Configuration Parameter Values in the XCO FileParameter Values in the XCO File TBI Output GenerationDesign Overview Designing with the CoreDesigning with the Core Design Overview 1000BASE-X Standard with TBI Example DesignExample Design Performing the Sgmii Standard Sgmii Standard Using a RocketIO Transceiver Example Design4Example Design Performing the Sgmii Standard Sgmii Standard with TBI Transceiver Example DesignDesign Guidelines Generate the CoreExamine the Example Design Provided with the Core Simulate and Download your Design Write an HDL ApplicationSynthesize your Design Create a BitstreamMake Only Allowed Modifications Recognize Timing Critical SignalsKeep it Registered Use Supported Design FlowsUsing the Client-side Gmii Data Path Gmii TransmissionNormal Frame Transmission Normal Frame Reception Error PropagationUsing the Client-side Gmii Data Path Gmii ReceptionNormal Frame Reception with Extension Field Frame Reception with ErrorsBit1 Link Synchronization Statusvector40 signalsFalse Carrier Bit0 Link StatusGmii Transmission Bits42 Code Group Reception IndicatorsGmii Reception Megabit per Second Frame Transmission Designing with Client-side Gmii for the Sgmii StandardOverview Gigabit per Second Frame TransmissionMegabit per Second Frame Reception Gigabit per Second Frame ReceptionGmii Transmitter Logic Using the Gmii as an Internal ConnectionUsing the Gmii as an Internal Connection Implementing External Gmii14GMII Transmitter Logic Virtex-II Pro and Virtex-II DevicesImplementing External Gmii Spartan-3, Spartan-3E and Spartan-3A Devices16External Gmii Transmitter Logic for Virtex-4 Devices Virtex-4 Devices17External Gmii Transmitter Logic for Virtex-5 Devices Virtex-5 DevicesGmii Receiver Logic 18External Gmii Receiver Logic Using the Client-side Gmii Data Path Ten-Bit Interface Ten-Bit-Interface LogicTransmitter Logic Receiver Logic Virtex-II and Virtex-II Pro DevicesTen-Bit Interface 2Ten-Bit-Interface Receiver Logic Ten-Bit-Interface LogicComponentnameblock Block Level from example design Method Idelay Iodelay IOB Logic Ibufg 7Alternate Ten-Bit Interface Receiver Logic Virtex-5 Devices Clock Sharing across Multiple Cores with TBI Clock Sharing across Multiple Cores with TBITen-Bit Interface 1000BASE-X with RocketIO Transceivers RocketIO Transceiver LogicVirtex-II Pro Devices 11000BASE-X Connection to a Virtex-II Pro MGT 1000BASE-X with RocketIO TransceiversRocketIO Transceiver Logic Virtex-4 FX Devices21000BASE-X Connection to Virtex-4 MGT Virtex-5 RocketIO GTP Wizard Virtex-5 LXT and SXT Devices31000BASE-X Connection to Virtex-5 GTP Transceivers Virtex-5 RocketIO GTX Wizard Virtex-5 FXT Devices41000BASE-X Connection to Virtex-5 GTX Transceivers Clock Sharing Across Multiple Cores with RocketIO Clock Sharing Across Multiple Cores with RocketIOVirtex-4 FX Devices Componentname block Virtex-5 LXT and SXT Devices Ibufgds Virtex-5 FXT Devices DCM 1000BASE-X with RocketIO Transceivers Selecting the Buffer Implementation from the GUI Receiver Elastic Buffer ImplementationsAnalysis Requirement for the Fpga Fabric Rx Elastic BufferReceiver Elastic Buffer Implementations RocketIO Rx Elastic BufferClosely Related Clock Sources RocketIO Logic using the RocketIO Rx Elastic BufferRocketIO Logic with the Fabric Rx Elastic Buffer RocketIO Logic with the Fabric Rx Elastic Buffer3SGMII Connection to a Virtex-II Pro RocketIO Transceiver Virtex-4 Devices for Sgmii or Dynamic Standards Switching 4SGMII Connection to a Virtex-4 MGT Ethernet 1000BASE-X PCS/PMA or Sgmii 103 5SGMII Connection to a Virtex-5 RocketIO GTP Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 105 6SGMII Connection to a Virtex-5 RocketIO GTX Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 107 108 Ethernet 1000BASE-X PCS/PMA or Sgmii 109 Sgmii Ethernet 1000BASE-X PCS/PMA or Sgmii 111 112 Ethernet 1000BASE-X PCS/PMA or Sgmii 113 114 Configuration and Status Mdio Management InterfaceMdio Bus System Configuration and Status Mdio Transactions1Abbreviations and Terms Mdio Management Interface 1Abbreviations and Terms Mdio AddressingWrite Transaction Read TransactionConnecting the Mdio to an External STA Connecting the Mdio to an Internally Integrated STA2MDIO Registers for 1000BASE-X with Auto-Negotiation 1000BASE-X Standard Using the Optional Auto-NegotiationManagement Registers Management RegistersRegister 0 Control Register Mdio Register 0 Control Register3Control Register Register LSB Management Registers 3Control Register RegisterRegister 1 Status Register Mdio Register 1 Status Register4Status Register Register Registers 2 and 3 PHY Identifiers Management Registers 4Status Register RegisterRegisters 2 and 3 PHY Identifiers Auto-Negotiation Advertisement Register Register Configuration and Status 5PHY Identifier Registers 2Register 4 Auto-Negotiation Advertisement Mdio Register 4 Auto-Negotiation AdvertisementMdio Register 5 Auto-Negotiation Link Partner Base Register 5 Auto-Negotiation Link Partner Base8Auto-Negotiation Expansion Register Register Register 6 Auto-Negotiation ExpansionRegister 7 Next Page Transmit Mdio Register 6 Auto-Negotiation ExpansionRegister 8 Next Page Receive Mdio Register 8 Next Page Receive10Auto-Negotiation Next Page Receive Register Register 15 Extended Status Mdio Register 15 Extended Status Register11Extended Status Register Register 13MDIO Registers for 1000BASE-X without Auto-Negotiation 1000BASE-X Standard Without the Optional Auto-Negotiation14Control Register Register 15Status Register Register Management Registers 14Control Register RegisterConfiguration and Status 15Status Register Register Mdio Register 15 Extended Status Registers 2 and 3 Phy IdentifierMdio Registers 2 and 3 PHY Identifier 16PHY Identifier Registers 2Configuration and Status 17Extended Status Register Mdio Register 0 Sgmii Control Sgmii Standard Using the Optional Auto-NegotiationRegister 0 Sgmii Control 18MDIO Registers for 1000BASE-X with Auto-NegotiationConfiguration and Status 19SGMII Control Register 20SGMII Status Register Register 1 Sgmii StatusManagement Registers 19SGMII Control Register Mdio Register 1 Sgmii StatusConfiguration and Status 20SGMII Status Register 22SGMII Auto-Negotiation Advertisement Register Register 4 Sgmii Auto-Negotiation Advertisement21PHY Identifier Registers 2 Mdio Register 4 Sgmii Auto-Negotiation AdvertisementMdio Register 5 Sgmii Auto-Negotiation Link Partner Ability Register 5 Sgmii Auto-Negotiation Link Partner AbilityRegister 7 Sgmii Auto-Negotiation Next Page Transmit Register 6 Sgmii Auto-Negotiation ExpansionRegister 8 Sgmii Next Page Receive Mdio Register 8 Sgmii Next Page Receive26SGMII Auto-Negotiation Next Page Receive Register Register 15 Sgmii Extended Status Mdio Register 15 Sgmii Extended Status27SGMII Extended Status Register Register Register 16 Sgmii Auto-Negotiation Interrupt Control Mdio Register 16 Sgmii Auto-Negotiation Interrupt Control28SGMII Auto-Negotiation Interrupt Control Register 29MDIO Registers for 1000BASE-X with Auto-Negotiation Sgmii Standard without the Optional Auto-NegotiationConfiguration and Status 30SGMII Control Register 31SGMII Status Register Management Registers 30SGMII Control RegisterConfiguration and Status 31SGMII Status Register 33SGMII Auto-Negotiation Advertisement Register 32PHY Identifier Registers 234SGMII Extended Status Register Register Both 1000BASE-X and Sgmii StandardsOptional Configuration Vector Optional Configuration VectorRegister 17 Vendor-specific Standard Selection Register Signal Direction Clock Description Domain 36Optional Configuration and Status VectorsOverview of Operation Auto-NegotiationAuto-Negotiation Sgmii Standard Overview of OperationSgmii Auto-Negotiation Simulating Auto-Negotiation Setting the Configurable Link TimerUsing the Auto-Negotiation Interrupt 1000BASE-X StandardTypical Application Dynamic Switching of 1000BASE-X and Sgmii StandardsOperation of the Core Selecting the Power-On / Reset StandardSwitching the Standard Using Mdio Setting the Auto-Negotiation Link TimerOperation of the Core 160 Required Constraints Constraining the CoreConstraining the Core Setting MGT AttributesMGT Transceiver Placement Constraints Clock Period Constraints# Enmcommaalign Required Constraints1Local Clock Place and Route for Top MGT Virtex-4 RocketIO MGTs for 1000BASE-X ConstraintsMGT Placement Constraints Setting MGT Transceiver AttributesSetting GTP Transceiver Attributes Ethernet 1000BASE-X PCS/PMA or Sgmii 167 UG155 March 24 Ten-Bit Interface Constraints Setting GTX Transceiver AttributesTen-Bit Interface IOB Constraints 1Input TBI Timing Symbol Min Max Units TBI Input Setup/Hold TimingVirtex-4 Devices Virtex-5 Devices Constraints When Implementing an External GmiiGmii IOB Constraints 2Input Gmii Timing Symbol Min Max Units Gmii Input Setup/Hold TimingEthernet 1000BASE-X PCS/PMA or Sgmii 175 Understanding Timing Reports for Setup/Hold Timing Devices Other Than Virtex-4 or Virtex-5Virtex-4 or Virtex-5 Devices 4Timing Report Setup/Hold Illustration 178 Integrating with the 1-Gigabit Ethernet MAC Core Interfacing to Other CoresMAC Interfacing to Other CoresIntegrating with the 1-Gigabit Ethernet MAC Core Virtex-II Pro Devices182 GTP Virtex-5 LXT and SXT DevicesClkdv Virtex-5 FXT DevicesIntegrating with the Tri-Mode Ethernet MAC Core Integrating with the Tri-Mode Ethernet MAC Core186 IOB Logic 188 Ethernet 1000BASE-X PCS/PMA or Sgmii 189 190 8Tri-Speed Ethernet MAC Extended to Use an Sgmii in Virtex-4 192 Ethernet 1000BASE-X PCS/PMA or Sgmii 193 194 Ethernet 1000BASE-X PCS/PMA or Sgmii 195 196 Loopback Power ManagementSpecial Design Considerations Startup SequencingSpecial Design Considerations Core with RocketIO TransceiverLoopback 200 Synthesis Using the Simulation ModelImplementing the Design Pre-implementation SimulationMapping the Design ImplementationXST Verilog Generating the Xilinx NetlistGenerating a Bitstream Using the ModelPost-Implementation Simulation Static Timing AnalysisVirtex-5 Devices Other Implementation InformationHardware Verification Core Verification, Compliance, and InteroperabilityVerification Simulation206 Transmit Path Latency Core LatencyCore Latency Latency for 1000BASE-X PCS with TBILatency for Sgmii Calculating the DCM Fixed Phase Shift Value Requirement for DCM Phase ShiftingFinding the Ideal Phase Shift Value for Your System Appendix C Calculating the DCM Fixed Phase Shift Value Introduction 1000BASE-X State MachinesStart of Frame Encoding Even Transmission CaseAppendix D 1000BASE-X State Machines Reception of the Even Case Odd Transmission CaseStart of Frame Encoding Reception of the Odd Case End of Frame Encoding Preamble ShrinkageEnd of Frame Encoding 216 Ethernet 1000BASE-X PCS/PMA or Sgmii 217 218 Rx Elastic Buffer Specifications Rx Elastic Buffers Depths and Maximum Frame SizesRocketIO Rx Elastic Buffers Virtex-II Pro and Virtex-5 Devices Appendix E Rx Elastic Buffer SpecificationsRx Elastic Buffers Depths and Maximum Frame Sizes Virtex-4 FXFigure E-2Elastic Buffer Size for all RocketIO families Sgmii Fabric Rx Elastic BufferFor Sgmii / Dynamic Switching TBI Rx Elastic BufferFor 1000BASE-X Idle Character Removal at 1Gbps 1000BASE-X and Sgmii Clock CorrectionIdle Character Removal at 100 Mbps Sgmii Idle Character Removal at 10 Mbps SgmiiClock Correction Maximum Frame Sizes for Sustained Frame Reception Jumbo Frame ReceptionRocketIO Sgmii Fabric Buffer General Checks Problems with the MdioProblems with Data Reception or Transmission Debugging GuideProblems with Auto-Negotiation Problems in Obtaining a Link Auto-Negotiation DisabledAppendix F Debugging Guide Debugging Problems with a High Bit Error RateSymptoms Problems with a High Bit Error RateRocketIO Transceiver Specific Checks