Xilinx Ethernet 1000BASE-X PCS/PMA or Sgmii with Ten-Bit-Interface, RocketIO Interface Block

System Overview

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Optional PCS Management Registers

Configuration and status of the core, including access to and from the optional Auto- Negotiation function, uses the 1000BASE-X PCS Management Registers defined in IEEE

802.3clause 37. These registers are accessed through the serial Management Data Input/Output Interface (MDIO), defined in IEEE 802.3 clause 22, as if it were an externally connected PHY.

The PCS Management Registers may be omitted from the core when the core is performing the 1000BASE-X standard. In this situation, configuration and status of the core is made possible with the use of an alternative configuration vector and a status signal.

When the core is performing the SGMII standard, the PCS Management Registers become mandatory and information in the registers takes on a different interpretation. For more information, see “Management Registers” in Chapter 9.

RocketIO Interface Block

The RocketIO Interface Block enables the core to connect to a Virtex-II Pro, Virtex-4, or Virtex-5 FPGA RocketIO transceiver.

Ethernet 1000BASE-X PCS/PMA or SGMII with Ten-Bit-Interface

The Ethernet 1000BASE-X PCS/PMA or SGMII core, when used with the Ten-Bit Interface (TBI), allows you to implement only the 1000BASE-X PCS sublayer.

	LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII Core
		PCS Transmit Engine	8B/10B
			Encoder
GMII	BlockGMII	Optional		BlockTBI	IOBs	TBI
to MAC
		Atuo-negotiation				to PMA
						Sublayer
		PCS Receive Engine	8B/10B	RX
				Elastic
		and Synchronization	Decoder
				Buffer
MDIO	Optional PCS
	Management
Interface
	Figure 2-2:	Functional Block Diagram with a Ten-Bit Interface

The optional TBI can be used in place of the RocketIO transceiver to provide a parallel interface for connection to an external PMA SERDES device. In this implementation, additional logic blocks are required to replace some of the RocketIO transceiver functionality. These are shown in the surrounded by the dotted line box in Figure 2-2and are described in the following sections. The other blocks are described previously in this document.

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 25

UG155 March 24, 2008