Xilinx 1000BASE-X manual Auto-Negotiation

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Chapter 6: The Ten-Bit Interface

Figure 6-1:Ten-Bit Interface Transmitter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 6-2:Ten-Bit-Interface Receiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 6-3:TBI Receiver Logic for Spartan-3, Spartan-3E, and Spartan-3A Devices. . . . . . . . . . . . . 72

Figure 6-4:Ten-Bit Interface Receiver Logic - Virtex-4 Device (Example Design) . . . . . . . . . . . . . . 73

Figure 6-5:Alternate Ten-Bit Interface Receiver Logic for Virtex-4 Devices . . . . . . . . . . . . . . . . . . . 74

Figure 6-6:Ten-Bit Interface Receiver Logic - Virtex-5 Device (Example Design) . . . . . . . . . . . . . . 75

Figure 6-7:Alternate Ten-Bit Interface Receiver Logic - Virtex-5 Devices . . . . . . . . . . . . . . . . . . . . . 76

Figure 6-8:Clock Management, Multiple Core Instances with Ten-Bit Interface . . . . . . . . . . . . . . . 77

Chapter 7: 1000BASE-X with RocketIO Transceivers

Figure 7-1:1000BASE-X Connection to a Virtex-II Pro MGT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 7-2:1000BASE-X Connection to Virtex-4 MGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 7-3:1000BASE-X Connection to Virtex-5 GTP Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 7-4:1000BASE-X Connection to Virtex-5 GTX Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 7-5:Clock Management: Two Core Instances, Virtex-II Pro

MGTs for 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 7-6:Clock Management - Multiple Core Instances, MGTs for 1000BASE-X . . . . . . . . . . . . . 89 Figure 7-7:Clock Management - Multiple Core Instances, Virtex-5 RocketIO GTP

Transceivers for 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 7-8:Clock Management - Multiple Core Instances, Virtex-5 RocketIO GTX

Transceivers for 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers

Figure 8-1:SGMII Implementation using Separate Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 8-2:SGMII Implementation using Shared Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 8-3:SGMII Connection to a Virtex-II Pro RocketIO Transceiver. . . . . . . . . . . . . . . . . . . . . . 100

Figure 8-4:SGMII Connection to a Virtex-4 MGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 8-5:SGMII Connection to a Virtex-5 RocketIO GTP Transceiver . . . . . . . . . . . . . . . . . . . . . 104

Figure 8-6:SGMII Connection to a Virtex-5 RocketIO GTX Transceiver . . . . . . . . . . . . . . . . . . . . . 106

Figure 8-7:Clock Management with Multiple Core Instances with Virtex-II Pro

RocketIO Transceivers for SGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 8-8:Clock Management with Multiple Core Instances with Virtex-4 MGTs for SGMII . 110 Figure 8-9:Clock Management with Multiple Core Instances with Virtex-5 GTP

RocketIO Transceivers for SGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 8-10:Clock Management with Multiple Core Instances with Virtex-5 GTX

RocketIO Transceivers for SGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Chapter 9: Configuration and Status

Figure 9-1:A Typical MDIO-managed System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 9-2:MDIO Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 9-3:MDIO Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 9-4:Creating an External MDIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 9-5:Dynamic Switching (Register 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Chapter 10: Auto-Negotiation
Figure 10-1:1000BASE-XAuto-Negotiation Overview	153
Figure 10-2:SGMII Auto-Negotiation	155

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UG155 March 24, 2008