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Chapter 2: Core Architecture
8B/10B Encoder
8B10B encoding, as defined in IEEE 802.3 (Tables
8B/10B Decoder
8B10B decoding, as defined in IEEE 802.3 (Table
Receiver Elastic Buffer
The Receiver Elastic Buffer enables the
TBI Block
The core provides a TBI interface that should be routed to device IOBs to provide an off- chip TBI.
Core Interfaces
All ports of the core are internal connections in FPGA fabric. An HDL example design (delivered with the core) connects the core, where appropriate, to a RocketIO transceiver, and/or add IBUFs, OBUFs, and IOB
All clock management logic is placed in this example design, allowing you more flexibility in implementation (such as designs using multiple cores). This example design is provided in both VHDL and Verilog. For more information, see the Ethernet
Figure 2-3 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using a RocketIO transceiver with the optional PCS Management Registers. The signals shown in the Auto-Negotiation box included only when the core includes the Auto-Negotiation
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| UG155 March 24, 2008 |