Xilinx 1000BASE-X manual Setting GTP Transceiver Attributes

R

Chapter 12: Constraining the Core

Virtex-4 RocketIO MGTs for SGMII or Dynamic Standards Switching Constraints

All the constraints described in the section “Virtex-4 RocketIO MGTs for 1000BASE-X Constraints.” In addition, if the FPGA Fabric Rx Elastic Buffer is selected, an extra clock period constraint of 16 ns is required for rxrecclk1.

With the MGT Rx Elastic Buffer bypassed, rxrecclk1 is provided by the MGT to the FPGA fabric for the recovered receiver data signals leaving the transceiver. This data is then written into the replacement Rx Elastic Buffer implemented in the FPGA fabric. See “Virtex-4 Devices for SGMII or Dynamic Standards Switching,” page 101.

The following UCF syntax shows the necessary constraint being applied to GT11 A.

#***********************************************************

#	PCS/PMA Clock period Constraints for	the GT11 A	*
#	recovered clock: please do not relax		*

#***********************************************************

NET "core_wrapper/rocketio/rxrecclk10" TNM_NET = "rxrecclk10";

TIMESPEC "ts_rxrecclk10" = PERIOD "rxrecclk10" 16 ns;

Virtex-5 RocketIO GTP Transceivers for 1000BASE-X Constraints

The constraints defined in this section are implemented in the UCF for the example designs delivered with the core. Sections from the UCF are copied into the following descriptions to serve as examples, and should be studied with the HDL source code for the example design. See also “Virtex-5 LXT and SXT Devices” in Chapter 7.

Clock Period Constraints

The clkin clock is provided to the GTP transceiver. It is a high-quality reference clock with a frequency of 125 MHz and should be constrained.

The refclkout clock is provided by the GTP for use in the FPGA fabric, which is then connected to global clock routing to produce the usrclk2 signal. This is the main 125 MHz clock used by all core logic and must be constrained.

The following UCF syntax shows these constraints being applied.

#***********************************************************

# PCS/PMA Clock period Constraints: please do not relax * #***********************************************************

NET "*clkin" TNM_NET = "clkin";

TIMESPEC "TS_clkin" = PERIOD "clkin" 8 ns HIGH 50 %;

NET "*refclkout" TNM_NET = "refclkout";

TIMESPEC "TS_refclkout" = PERIOD "refclkout" 8 ns HIGH 50 %;

Setting GTP Transceiver Attributes

The Virtex-5 GTP transceiver has many attributes that are set directly from HDL source code for the transceiver wrapper file delivered with the example design. These can be found in the rocketio_wrapper_gtp_tile.vhd file (for VHDL design entry) or the rocketio_wrapper_gtp_tile.v file (for Verilog design entry): these files were generated using the GTP Transceiver Wizard - to change the attributes, re-run the Wizard. See “Virtex-5 RocketIO GTP Wizard” in Chapter 7.

166	www.xilinx.com	Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
		UG155 March 24, 2008