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Core Interfaces
R
Configuration Vector (Optional)
Table
Table
Signal | Direction | Description |
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configuration_vector[3:0]1 | Input | Bit[0]: Reserved (currently unused) |
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| Bit[1]: Loopback Control |
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| • When the core with RocketIO transceiver is |
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| used, the core is placed in internal loopback |
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| mode. |
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| • With the TBI version, Bit 1 is connected to |
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| ewrap. When set to ‘1,’ this indicates to the |
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| external PMA module to enter loopback mode. |
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| Bit[2]: Power Down |
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| • When the RocketIO transceiver is used (when |
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| set to ‘1’), the MGT is placed in a low power |
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| state. A reset must be applied to clear. |
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| • With the TBI version this bit is unused. |
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| Bit[3]: Isolate |
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| When set to ‘1,’ the GMII should be electrically |
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| isolated. When set to ‘0,’ normal operation is |
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| enabled. |
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1.This signal is synchronous to the core’s internal 125 MHz reference clock. This is userclk2 when the core is used with the RocketIO transceiver; this is gtx_clk when the core is used with TBI.
Auto-Negotiation Signal Pinout
Table
Table 2-5: Optional Auto-Negotiation Interface Signal Pinout
Signal | Direction | Description |
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link_timer_value[8:0]1 | Input | Used to configure the duration of the Auto- |
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| Negotiation Link Timer period. The duration of this |
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| timer is set to the binary number input into this port |
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| multiplied by 4096 clock periods of the 125 MHz |
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| reference clock (8 ns). It is expected that this signal |
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| will be tied off to a logical value. |
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| This port is replaced when using the dynamic |
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| switching mode. |
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an_interrupt1 | Output | Active high interrupt to signal the completion of an |
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| |
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| enabled/disabled and cleared by writing to the |
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| appropriate PCS Management Register. |
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1.These signals are synchronous to the core’s internal 125 MHz reference clock. This is userclk2 when the core is used with the RocketIO transceiver; this is gtx_clk when the core is used with TBI.
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