Xilinx 1000BASE-X manual Management Registers 30SGMII Control Register, 31SGMII Status Register

Management Registers

Table 9-30:SGMII Control (Register 0) (Continued)

R

Bit(s)	Name	Description	Attributes	Default
				Value
0.5	Unidirectiona	Enable transmit regardless of	read/ write	0
	l Enable	whether a valid link has been
		established
0.4:0	Reserved	Always return 0s , writes ignored	returns 0s	00000

Register 1: SGMII Status

MDIO Register 1: SGMII Status

15		14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reg 1
	100BASE-T4	100BASE-X FULL DUPLEX	100BASE-X HALF DUPLEX	10Mb/s FULL DUPLEX	10Mb/s HALF DUPLEX	100BASE-T2 FULL DUPLEX	100BASE-T2 HALF DUPLEX	EXTENDED STATUS	UNIDIRECTIONAL ANILITY	MF PREAMBLE SUPPRESSION	AUTO-NEG COMPLETE	REMOTE FAULT	AUTO-NEG ABILITY	LINK STATUS	JABBER DETECT	EXTENDED CAPABILITY

Table 9-31:SGMII Status (Register 1)

Bit(s)	Name	Description	Attributes	Default
				Value
1.15	100BASE-T4	Always returns a ‘0’ for this bit because	returns 0	0
		100BASE-T4 is not supported
1.14	100BASE-X Full	Always returns a ‘0’ for this bit because	returns 0	0
	Duplex	100BASE-X Full Duplex is not supported
1.13	100BASE-X Half	Always returns a ‘0’ for this bit because	returns 0	0
	Duplex	100BASE-X Half Duplex is not supported
1.12	10 Mbps Full Duplex	Always returns a ‘0’ for this bit because 10	returns 0	0
		Mbps Full Duplex is not supported
1.11	10 Mbps Half Duplex	Always returns a ‘0’ for this bit because 10	returns 0	0
		Mbps Half Duplex is not supported
1.10	100BASE-T2 Full	Always returns a ‘0’ for this bit because	returns 0	0
	Duplex	100BASE-T2 Full Duplex is not supported
1.9	100BASE-T2 Half	Always returns a ‘0’ for this bit because	returns 0	0
	Duplex	100BASE-T2 Half Duplex is not
		supported
1.8	Extended Status	Always returns a ‘1’ for this bit to indicate	returns 1	1
		the presence of the Extended Register
		(Register 15)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 147

UG155 March 24, 2008