
RocketIO Transceiver Logic
R
Virtex-5 LXT and SXT Devices
The core is designed to integrate with the
Note: A small logic shim (included in the
A GTP tile consists of a pair of transceivers. For this reason, the GTP transceiver wrapper delivered with the core always contains two GTP instantiations, even if only a single GTP transceiver tile is in use. Figure
The 125 MHz differential reference clock is routed directly to the GTP transceiver. The GTP transceiver is configured to output a version of this clock on the REFCLKOUT port and after placement onto global clock routing, can be used by all core logic. This clock is input back into the GTP transceiver on the user interface clock ports rxusrclk, rxusrclk2, txusrclk, and txusrclk2.
See also
Virtex-5 RocketIO GTP Wizard
The two wrapper files immediately around the GTP transceiver pair,
rocketio_wrapper_gtp_tile and rocketio_wrapper_gtp (see Figure
The CORE Generator log file (XCO file) which was created when the RocketIO GTP Wizard project was generated is available in the following location:
<project_directory>/<component_name>/example_design/transceiver/ rocketio_wrapper_gtp.xco
This file can be used as an input to the CORE Generator to regenerate the RocketIO wrapper files. The XCO file itself contains a list of all of the GTP Wizard attributes which were used. For further information, please refer to the
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