Xilinx 1000BASE-X Rx Elastic Buffer Specifications

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 219
UG155 March 24, 2008
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Appendix E
Rx Elastic Buffer Specifications
This appendix is intended to se rve as a reference f or the Rx Elastic B uffer sizes used i n the
core, and the related maximum frame sizes that can be used without causing a buffer
underflow or overflow error.
Throughout this appendix, all analyses are based on 100 ppm clock tolerances on both
sides of the elastic buffer (200 ppm total difference). This corresponds to the Ethernet clock
tolerance specification.
Introduction
The need for an Rx Elastic Buffer is illustrated in “The Requirement for the FPGA Fabric Rx
Elastic Buffer” in Chapter 8. The analysis included in this chapter shows that for standard
Ethernet clock tolerances (100 ppm) there can be a maximum difference of one clock edge
every 5000 clock periods of the nominal 125 MHz clock frequency.
This slight difference in clock frequency on either side of the buffer will accumulate and
either start to fill or empty the Rx Elastic Buffer over time. The Rx Elastic buffer copes with
this by performing clock correction during the interframe gaps by either inserting or
removing Idle characters. The Rx Elastic Buffer will always attempt to restore the buffer
occupancy to the half full level during an interframe gap. See “Clock Correction,” page
224.
Rx Elastic Buffers: Depths and Maximum Frame Sizes
RocketIO Rx Elastic Buffers
Figure E-1 illustrates the RocketIO transceiver Rx Elastic Buffer depths and thresholds in
Virtex-II Pro, Virtex-4 FX, Virtex-5 LXT, SXT and FXT families. Each FIFO word
corresponds to a single character of data (equivalent to a single byte of data following
8B10B decoding).