Xilinx manual Ethernet 1000BASE-X PCS/PMA or Sgmii 167 UG155 March 24

Required Constraints

R

Virtex-5 RocketIO GTP Transceivers for SGMII or Dynamic Standards Switching Constraints

If the core is generated to use the GTP Rx Elastic Buffer, all of the constraints apply, as defined in “Clock Period Constraints,” page 166. However, if the FPGA Fabric Rx Elastic Buffer is selected, an extra clock period constraint of 8 ns is required for rxrecclk: with the GTP Rx Elastic Buffer bypassed, rxrecclk is provided by the GTP transceiver to the FPGA fabric for the recovered receiver data signals leaving the transceiver. This data is then written into the replacement Rx Elastic Buffer implemented in the FPGA fabric. See “Virtex-5 LXT or SXT Devices for SGMII or Dynamic Standards Switching,” page 103 for more information about this logic.

The following UCF syntax shows the necessary constraint being applied to the rxrecclk signal sourced from GTP 0.

#***********************************************************

#	PCS/PMA Clock period Constraints for	the GTP 0	*
#	recovered clock: please do not relax		*

#***********************************************************

NET "core_wrapper/rocketio/rxrecclk0" TNM_NET = "rxrecclk0";

TIMESPEC "ts_rxrecclk0" = PERIOD "rxrecclk0" 8 ns;

Setting GTP Transceiver Attributes

Additionally, if the FPGA Fabric Rx Elastic Buffer is selected, then the attributes of the Virtex-5 GTP transceiver which are set directly from HDL source code do differ from the standard case. These can be found in the rocketio_wrapper_gtp_tile.vhd file (for VHDL design entry) or the rocketio_wrapper_gtp_tile.v file (for Verilog design entry): these files were generated using the GTP RocketIO Wizard - to change the attributes, re-run the Wizard. See “Virtex-5 RocketIO GTP Wizard” in Chapter 8.

Virtex-5 RocketIO GTX Transceivers for 1000BASE-X Constraints

The constraints defined in this section are implemented in the UCF for the example designs delivered with the core. Sections from the UCF are copied into the following descriptions to serve as examples, and should be studied with the HDL source code for the example design. See also “Virtex-5 FXT Devices” in Chapter 7.

Clock Period Constraints

The clkin clock is provided to the GTX transceiver. It is a high-quality reference clock with a frequency of 125 MHz and should be constrained.

The refclkout clock is provided by the GTX for use in the FPGA fabric–this is the main 125MHz clock reference source for the FPGA fabric and should be constrained. This is then connected to a DCM. The ports CLK0 (125MHz) and CLKDV (62.5MHz) of this DCM are then placed onto global clock routing to produce the usrclk2 and usrclk clock signals respectively. The Xilinx tools will trace the refclkout constraint through the DCM and automatically generate clock period constraints for the DCM output clocks. So constraints usrclk2 and usrclk do not need to be manually applied.

The following UCF syntax shows these constraints being applied.

#***********************************************************

# PCS/PMA Clock period Constraints: please do not relax		*
#***********************************************************
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1	www.xilinx.com	167
UG155 March 24, 2008