Implementation, XST Verilog, Mapping the Design | Xilinx 1000BASE-X

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Chapter 15: Implementing the Design

See the XST User Guide for more information on creating project and synthesis script files, and running the xst program.

XST - Verilog

There is a module declaration for the Ethernet 1000BASE-X PCS/PMA or SGMII core in the CORE Generator project directory:

<component_name>/implement/<component_name>_mod.v

Use this module to help instance the Ethernet 1000BASE-X PCS/PMA or SGMII core into your Verilog source.

After the entire design is complete, do the following:

•Generate an XST project file top_level_module_name.prj listing all user source code files.

Make sure to include the following as the first two files in the project list.

%XILINX%/verilog/src/iSE/unisim_comp.v

and

<component_name>/implement/component_name_mod.v

•Generate an XST script file top_level_module_name.scr containing your required synthesis options.

To synthesize the design, run:

$ xst -ifntop_level_module_name.scr

See the XST User Guide for more information on creating project and synthesis script files, and running the xst program.

Implementation

Generating the Xilinx Netlist

To generate the Xilinx netlist, the ngdbuild tools is used to translate and merge the individual design netlists into a single design database—the NGD file. Also merged at this stage is the UCF for the design. An example of the ngdbuild command is:

$ ngdbuild -sdpath_to_core_netlist -sdpath_to_user_synth_results \

-uctop_level_module_name.ucf top_level_module_name

Mapping the Design

To map the logic gates of the user design netlist into the CLBs and IOBs of the FPGA, run the map command. The map command writes out a physical design to an NCD file. An example of the map command is:

$ map -otop_level_module_name_map.ncd top_level_module_name.ngd \

top_level_module_name.pcf

Placing and Routing the Design

The par command must be executed to place and route the user’s design logic components (mapped physical logic cells) within an NCD file, in accordance with the

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Xilinx 1000BASE-X manual Implementation, XST Verilog, Generating the Xilinx Netlist, Mapping the Design

Contents

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or Sgmii UG155 March 24 Revision History Date Doc Revision Version Table of Contents Using the Client-side Gmii Data Path Configuration and Status Interfacing to Other Cores Appendix C Calculating the DCM Fixed Phase Shift Value UG155 March 24 1Functional Block Diagram Using RocketIO Transceiver Schedule of Figures Auto-Negotiation Typical Application for Dynamic Switching 157 UG155 March 24 5Optional Auto-Negotiation Interface Signal Pinout Schedule of Tables 33SGMII Auto-Negotiation Advertisement Register 4 Guide Contents About This Guide Preface About This Guide ConventionsTypographical Convention Meaning or Use Example Online Document Conventions Meaning or Use Example Preface About This Guide About the Core Designs Using RocketIO TransceiversIntroduction Recommended Design Experience Feedback Additional Core ResourcesTechnical Support Ethernet 1000BASE-X PCS/PMA or Sgmii Core Document Feedback Introduction Core Architecture System Overview PCS Receive Engine and Synchronization Gmii BlockPCS Transmit Engine Optional Auto-Negotiation Block RocketIO Interface Block Ethernet 1000BASE-X PCS/PMA or Sgmii with Ten-Bit-InterfaceOptional PCS Management Registers System Overview 8B/10B Decoder Core Interfaces8B/10B Encoder Receiver Elastic Buffer Core Interfaces Core Architecture Core Interfaces Core Architecture Client Side Interface Gmii Pinout Ethernet 1000BASE-X PCS/PMA or Sgmii Common Signal Pinout 2Other Common Signals Direction Description Mdio Management Interface Pinout Optional MAC Auto-Negotiation Signal Pinout Configuration Vector Optional5Optional Auto-Negotiation Interface Signal Pinout Dynamic Switching Signal Pinout Physical Side Interface Ethernet 1000BASE-X PCS/PMA or Sgmii 1000BASE-X PCS with TBI Pinout GUI Interface Generating and Customizing the CoreComponent Name Core Functionality Select StandardGenerating and Customizing the Core Mdio Management Interface SGMII/Dynamic Standard Switching Elastic Buffer OptionsPhysical Interface Auto-Negotiation 3SGMII/Dynamic Standard Switching Options Screen Parameter Values in the XCO File RocketIO Tile ConfigurationParameter Values in the XCO File Output Generation TBI Designing with the Core Design Overview Designing with the Core 1000BASE-X Standard with TBI Example Design Design Overview Sgmii Standard Using a RocketIO Transceiver Example Design Example Design Performing the Sgmii Standard Sgmii Standard with TBI Transceiver Example Design 4Example Design Performing the Sgmii Standard Generate the Core Design GuidelinesExamine the Example Design Provided with the Core Create a Bitstream Write an HDL ApplicationSynthesize your Design Simulate and Download your Design Use Supported Design Flows Recognize Timing Critical SignalsKeep it Registered Make Only Allowed Modifications Gmii Transmission Using the Client-side Gmii Data PathNormal Frame Transmission Gmii Reception Error PropagationUsing the Client-side Gmii Data Path Normal Frame Reception Frame Reception with Errors Normal Frame Reception with Extension Field Bit0 Link Status Statusvector40 signalsFalse Carrier Bit1 Link Synchronization Bits42 Code Group Reception Indicators Gmii Transmission Gmii Reception Gigabit per Second Frame Transmission Designing with Client-side Gmii for the Sgmii StandardOverview Megabit per Second Frame Transmission Gigabit per Second Frame Reception Megabit per Second Frame Reception Implementing External Gmii Using the Gmii as an Internal ConnectionUsing the Gmii as an Internal Connection Gmii Transmitter Logic Virtex-II Pro and Virtex-II Devices 14GMII Transmitter Logic Spartan-3, Spartan-3E and Spartan-3A Devices Implementing External Gmii Virtex-4 Devices 16External Gmii Transmitter Logic for Virtex-4 Devices Virtex-5 Devices 17External Gmii Transmitter Logic for Virtex-5 Devices Gmii Receiver Logic 18External Gmii Receiver Logic Using the Client-side Gmii Data Path Ten-Bit-Interface Logic Ten-Bit InterfaceTransmitter Logic Virtex-II and Virtex-II Pro Devices Receiver LogicTen-Bit Interface Ten-Bit-Interface Logic 2Ten-Bit-Interface Receiver Logic Componentnameblock Block Level from example design Method Idelay Iodelay IOB Logic Ibufg 7Alternate Ten-Bit Interface Receiver Logic Virtex-5 Devices Clock Sharing across Multiple Cores with TBI Clock Sharing across Multiple Cores with TBI Ten-Bit Interface RocketIO Transceiver Logic 1000BASE-X with RocketIO TransceiversVirtex-II Pro Devices 1000BASE-X with RocketIO Transceivers 11000BASE-X Connection to a Virtex-II Pro MGT Virtex-4 FX Devices RocketIO Transceiver Logic 21000BASE-X Connection to Virtex-4 MGT Virtex-5 LXT and SXT Devices Virtex-5 RocketIO GTP Wizard 31000BASE-X Connection to Virtex-5 GTP Transceivers Virtex-5 FXT Devices Virtex-5 RocketIO GTX Wizard 41000BASE-X Connection to Virtex-5 GTX Transceivers Clock Sharing Across Multiple Cores with RocketIO Clock Sharing Across Multiple Cores with RocketIO Virtex-4 FX Devices Componentname block Virtex-5 LXT and SXT Devices Ibufgds Virtex-5 FXT Devices DCM 1000BASE-X with RocketIO Transceivers Receiver Elastic Buffer Implementations Selecting the Buffer Implementation from the GUI Requirement for the Fpga Fabric Rx Elastic Buffer Analysis RocketIO Rx Elastic Buffer Receiver Elastic Buffer Implementations RocketIO Logic using the RocketIO Rx Elastic Buffer Closely Related Clock Sources RocketIO Logic with the Fabric Rx Elastic Buffer RocketIO Logic with the Fabric Rx Elastic Buffer 3SGMII Connection to a Virtex-II Pro RocketIO Transceiver Virtex-4 Devices for Sgmii or Dynamic Standards Switching 4SGMII Connection to a Virtex-4 MGT Ethernet 1000BASE-X PCS/PMA or Sgmii 103 5SGMII Connection to a Virtex-5 RocketIO GTP Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 105 6SGMII Connection to a Virtex-5 RocketIO GTX Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 107 108 Ethernet 1000BASE-X PCS/PMA or Sgmii 109 Sgmii Ethernet 1000BASE-X PCS/PMA or Sgmii 111 112 Ethernet 1000BASE-X PCS/PMA or Sgmii 113 114 Mdio Management Interface Configuration and StatusMdio Bus System Mdio Transactions Configuration and Status1Abbreviations and Terms Read Transaction Mdio AddressingWrite Transaction Mdio Management Interface 1Abbreviations and Terms Connecting the Mdio to an Internally Integrated STA Connecting the Mdio to an External STA Management Registers 1000BASE-X Standard Using the Optional Auto-NegotiationManagement Registers 2MDIO Registers for 1000BASE-X with Auto-Negotiation Mdio Register 0 Control Register Register 0 Control Register3Control Register Register Management Registers 3Control Register Register LSB Mdio Register 1 Status Register Register 1 Status Register4Status Register Register Management Registers 4Status Register Register Registers 2 and 3 PHY IdentifiersRegisters 2 and 3 PHY Identifiers Mdio Register 4 Auto-Negotiation Advertisement Configuration and Status 5PHY Identifier Registers 2Register 4 Auto-Negotiation Advertisement Auto-Negotiation Advertisement Register Register Register 5 Auto-Negotiation Link Partner Base Mdio Register 5 Auto-Negotiation Link Partner Base Mdio Register 6 Auto-Negotiation Expansion Register 6 Auto-Negotiation ExpansionRegister 7 Next Page Transmit 8Auto-Negotiation Expansion Register Register Mdio Register 8 Next Page Receive Register 8 Next Page Receive10Auto-Negotiation Next Page Receive Register Mdio Register 15 Extended Status Register Register 15 Extended Status11Extended Status Register Register 1000BASE-X Standard Without the Optional Auto-Negotiation 13MDIO Registers for 1000BASE-X without Auto-Negotiation 14Control Register Register Management Registers 14Control Register Register 15Status Register Register Configuration and Status 15Status Register Register 16PHY Identifier Registers 2 Registers 2 and 3 Phy IdentifierMdio Registers 2 and 3 PHY Identifier Mdio Register 15 Extended Status Configuration and Status 17Extended Status Register 18MDIO Registers for 1000BASE-X with Auto-Negotiation Sgmii Standard Using the Optional Auto-NegotiationRegister 0 Sgmii Control Mdio Register 0 Sgmii Control Configuration and Status 19SGMII Control Register Mdio Register 1 Sgmii Status Register 1 Sgmii StatusManagement Registers 19SGMII Control Register 20SGMII Status Register Configuration and Status 20SGMII Status Register Mdio Register 4 Sgmii Auto-Negotiation Advertisement Register 4 Sgmii Auto-Negotiation Advertisement21PHY Identifier Registers 2 22SGMII Auto-Negotiation Advertisement Register Register 5 Sgmii Auto-Negotiation Link Partner Ability Mdio Register 5 Sgmii Auto-Negotiation Link Partner Ability Register 6 Sgmii Auto-Negotiation Expansion Register 7 Sgmii Auto-Negotiation Next Page Transmit Mdio Register 8 Sgmii Next Page Receive Register 8 Sgmii Next Page Receive26SGMII Auto-Negotiation Next Page Receive Register Mdio Register 15 Sgmii Extended Status Register 15 Sgmii Extended Status27SGMII Extended Status Register Register Mdio Register 16 Sgmii Auto-Negotiation Interrupt Control Register 16 Sgmii Auto-Negotiation Interrupt Control28SGMII Auto-Negotiation Interrupt Control Register Sgmii Standard without the Optional Auto-Negotiation 29MDIO Registers for 1000BASE-X with Auto-Negotiation Configuration and Status 30SGMII Control Register Management Registers 30SGMII Control Register 31SGMII Status Register Configuration and Status 31SGMII Status Register 32PHY Identifier Registers 2 33SGMII Auto-Negotiation Advertisement Register Both 1000BASE-X and Sgmii Standards 34SGMII Extended Status Register Register Optional Configuration Vector Optional Configuration VectorRegister 17 Vendor-specific Standard Selection Register 36Optional Configuration and Status Vectors Signal Direction Clock Description Domain Auto-Negotiation Overview of Operation Auto-Negotiation Overview of Operation Sgmii StandardSgmii Auto-Negotiation 1000BASE-X Standard Setting the Configurable Link TimerUsing the Auto-Negotiation Interrupt Simulating Auto-Negotiation Dynamic Switching of 1000BASE-X and Sgmii Standards Typical Application Setting the Auto-Negotiation Link Timer Selecting the Power-On / Reset StandardSwitching the Standard Using Mdio Operation of the Core Operation of the Core 160 Constraining the Core Required Constraints Clock Period Constraints Setting MGT AttributesMGT Transceiver Placement Constraints Constraining the Core Required Constraints # Enmcommaalign Virtex-4 RocketIO MGTs for 1000BASE-X Constraints 1Local Clock Place and Route for Top MGT Setting MGT Transceiver Attributes MGT Placement Constraints Setting GTP Transceiver Attributes Ethernet 1000BASE-X PCS/PMA or Sgmii 167 UG155 March 24 Setting GTX Transceiver Attributes Ten-Bit Interface Constraints Ten-Bit Interface IOB Constraints TBI Input Setup/Hold Timing 1Input TBI Timing Symbol Min Max Units Virtex-4 Devices Constraints When Implementing an External Gmii Virtex-5 Devices Gmii IOB Constraints Gmii Input Setup/Hold Timing 2Input Gmii Timing Symbol Min Max Units Ethernet 1000BASE-X PCS/PMA or Sgmii 175 Devices Other Than Virtex-4 or Virtex-5 Understanding Timing Reports for Setup/Hold TimingVirtex-4 or Virtex-5 Devices 4Timing Report Setup/Hold Illustration 178 Interfacing to Other Cores Integrating with the 1-Gigabit Ethernet MAC Core Interfacing to Other Cores MAC Virtex-II Pro Devices Integrating with the 1-Gigabit Ethernet MAC Core 182 Virtex-5 LXT and SXT Devices GTP Virtex-5 FXT Devices Clkdv Integrating with the Tri-Mode Ethernet MAC Core Integrating with the Tri-Mode Ethernet MAC Core 186 IOB Logic 188 Ethernet 1000BASE-X PCS/PMA or Sgmii 189 190 8Tri-Speed Ethernet MAC Extended to Use an Sgmii in Virtex-4 192 Ethernet 1000BASE-X PCS/PMA or Sgmii 193 194 Ethernet 1000BASE-X PCS/PMA or Sgmii 195 196 Startup Sequencing Power ManagementSpecial Design Considerations Loopback Core with RocketIO Transceiver Special Design Considerations Loopback 200 Pre-implementation Simulation Using the Simulation ModelImplementing the Design Synthesis Generating the Xilinx Netlist ImplementationXST Verilog Mapping the Design Static Timing Analysis Using the ModelPost-Implementation Simulation Generating a Bitstream Other Implementation Information Virtex-5 Devices Simulation Core Verification, Compliance, and InteroperabilityVerification Hardware Verification 206 Latency for 1000BASE-X PCS with TBI Core LatencyCore Latency Transmit Path Latency Latency for Sgmii Requirement for DCM Phase Shifting Calculating the DCM Fixed Phase Shift ValueFinding the Ideal Phase Shift Value for Your System Appendix C Calculating the DCM Fixed Phase Shift Value 1000BASE-X State Machines Introduction Even Transmission Case Start of Frame EncodingAppendix D 1000BASE-X State Machines Odd Transmission Case Reception of the Even CaseStart of Frame Encoding Reception of the Odd Case Preamble Shrinkage End of Frame EncodingEnd of Frame Encoding 216 Ethernet 1000BASE-X PCS/PMA or Sgmii 217 218 Rx Elastic Buffers Depths and Maximum Frame Sizes Rx Elastic Buffer SpecificationsRocketIO Rx Elastic Buffers Appendix E Rx Elastic Buffer Specifications Virtex-II Pro and Virtex-5 Devices Virtex-4 FX Rx Elastic Buffers Depths and Maximum Frame Sizes Sgmii Fabric Rx Elastic Buffer Figure E-2Elastic Buffer Size for all RocketIO families TBI Rx Elastic Buffer For Sgmii / Dynamic SwitchingFor 1000BASE-X Clock Correction Idle Character Removal at 1Gbps 1000BASE-X and Sgmii Idle Character Removal at 10 Mbps Sgmii Idle Character Removal at 100 Mbps SgmiiClock Correction Jumbo Frame Reception Maximum Frame Sizes for Sustained Frame ReceptionRocketIO Sgmii Fabric Buffer Debugging Guide Problems with the MdioProblems with Data Reception or Transmission General Checks Problems in Obtaining a Link Auto-Negotiation Disabled Problems with Auto-NegotiationAppendix F Debugging Guide Problems with a High Bit Error Rate Problems with a High Bit Error RateSymptoms Debugging RocketIO Transceiver Specific Checks