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Chapter 15: Implementing the Design
See the XST User Guide for more information on creating project and synthesis script files, and running the xst program.
XST - Verilog
There is a module declaration for the Ethernet
<component_name>/implement/<component_name>_mod.v
Use this module to help instance the Ethernet
After the entire design is complete, do the following:
•Generate an XST project file top_level_module_name.prj listing all user source code files.
Make sure to include the following as the first two files in the project list.
%XILINX%/verilog/src/iSE/unisim_comp.v
and
<component_name>/implement/component_name_mod.v
•Generate an XST script file top_level_module_name.scr containing your required synthesis options.
To synthesize the design, run:
$ xst
See the XST User Guide for more information on creating project and synthesis script files, and running the xst program.
Implementation
Generating the Xilinx Netlist
To generate the Xilinx netlist, the ngdbuild tools is used to translate and merge the individual design netlists into a single design
$ ngdbuild
Mapping the Design
To map the logic gates of the user design netlist into the CLBs and IOBs of the FPGA, run the map command. The map command writes out a physical design to an NCD file. An example of the map command is:
$ map
top_level_module_name.pcf
Placing and Routing the Design
The par command must be executed to place and route the user’s design logic components (mapped physical logic cells) within an NCD file, in accordance with the
202 | www.xilinx.com | Ethernet |
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| UG155 March 24, 2008 |