![](/images/new-backgrounds/1264492/264492141x1.webp)
Ten-Bit-Interface Logic
R
synchronous to pma_rx_clk0_bufg and pma_rx_clk1_bufg, respectively. These busses are then immediately registered inside the core on their respective clock.
component_name_block (Block Level from example design)
IOB LOGIC
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or SGMII LogiCORE | pma_rx_clk0_bufg | BUFG |
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| IBUFG |
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| pma_rx_clk0_ibufg | pma_rx_clk0 | |||
pma_rx_clk0 | (62.5 MHz) |
| IPAD | |||
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| IOB LOGIC |
| pma_rx_clk1_bufg | BUFG |
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| IBUFG |
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| pma_rx_clk1 | |
| (62.5 MHz) |
| pma_rx_clk1_ibufg | |||
pma_rx_clk1 |
| IPAD | ||||
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| IOB LOGIC |
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| IBUF |
| rx_code_group0_reg[0] |
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| rx_code_group[0] | |
rx_code_group0[0] | Q | D |
| IPAD | ||
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rx_code_group1[0] | rx_code_group1_reg[0] | Q | D |
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| rx_code_group_ibuf[0] | ||||
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Figure 6-2: Ten-Bit-Interface Receiver Logic
Ethernet | www.xilinx.com | 71 |