
Core Interfaces
R
Common Signal Pinout
Table
Table 2-2: Other Common Signals
Signal | Direction | Description |
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|
reset | Input | Asynchronous reset for the entire core. Active High. Clock |
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| domain is not applicable. |
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|
|
signal_detect | Input | Signal direct from PMD sublayer indicating the presence |
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| of light detected at the optical receiver. If set to ’1,’ |
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| indicates that the optical receiver has detected light. If set |
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| to ’0,’ this indicates the absence of light. |
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| If unused this signal should be set to ’1’to enable correct |
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| operation the core. Clock domain is not applicable. |
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|
|
status_vector[4:0]1 | Output | Bit[0]: Link Status |
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| Indicates the status of the link. |
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| • When high, the link is valid: synchronization of the link |
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| has been obtained and |
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| enabled) has successfully completed. |
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| • When low, a valid link has not been established. Either |
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| link synchronization has failed or |
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| present and enabled) has failed to complete. |
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| • When |
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| to Status Register Bit 1.2: Link Status. |
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| • When |
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| to status_vector Bit[1]. |
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| Bit[1]: Link Synchronization |
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| Indicates the state of the synchronization state machine |
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| (IEEE802.3 figure |
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| valid 8B10B code groups. This signal is similar to Bit[0] |
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| (Link Status), but is NOT qualified with |
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| • When high, link synchronization has been obtained and |
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| in the synchronization state machine, sync_status = |
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| OK. |
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| • When low, synchronization has failed. |
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| Bit[2]: RUDI(/C/) |
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| The core is receiving /C/ ordered sets |
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| Configuration sequences). |
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| Bit[3]: RUDI(/I/) |
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| The core is receiving /I/ ordered sets (Idles). |
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| Bit[4]: RUDI(INVALID) |
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| The core has received invalid data whilst receiving/C/ or |
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| /I/ ordered set. See “status_vector[4:0] signals” in |
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| Chapter 5 for more information. |
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|
|
1.These signals are synchronous to the core’s internal 125 MHz reference clock. This is userclk2 when the core is used with the RocketIO transceiver; this is gtx_clk when the core is used with TBI.
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