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Xilinx 1000BASE-X manual Common Signal Pinout, 2Other Common Signals Direction Description

Models: 1000BASE-X

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Core Interfaces

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Common Signal Pinout

Table 2-2describes the remaining signals common to all parameterizations of the core.

Table 2-2:Other Common Signals

Signal	Direction	Description

reset	Input	Asynchronous reset for the entire core. Active High. Clock
		domain is not applicable.

signal_detect	Input	Signal direct from PMD sublayer indicating the presence
		of light detected at the optical receiver. If set to ’1,’
		indicates that the optical receiver has detected light. If set
		to ’0,’ this indicates the absence of light.
		If unused this signal should be set to ’1’to enable correct
		operation the core. Clock domain is not applicable.

status_vector[4:0]1	Output	Bit[0]: Link Status
		Indicates the status of the link.
		• When high, the link is valid: synchronization of the link
		has been obtained and Auto-Negotiation (if present and
		enabled) has successfully completed.
		• When low, a valid link has not been established. Either
		link synchronization has failed or Auto-Negotiation (if
		present and enabled) has failed to complete.
		• When auto-negotiation is enabled this signal is identical
		to Status Register Bit 1.2: Link Status.
		• When auto-negotiation is disabled this signal is identical
		to status_vector Bit[1].
		Bit[1]: Link Synchronization
		Indicates the state of the synchronization state machine
		(IEEE802.3 figure 36-9) which is based on the reception of
		valid 8B10B code groups. This signal is similar to Bit[0]
		(Link Status), but is NOT qualified with Auto-Negotiation.
		• When high, link synchronization has been obtained and
		in the synchronization state machine, sync_status =
		OK.
		• When low, synchronization has failed.
		Bit[2]: RUDI(/C/)
		The core is receiving /C/ ordered sets (Auto-Negotiation
		Configuration sequences).
		Bit[3]: RUDI(/I/)
		The core is receiving /I/ ordered sets (Idles).
		Bit[4]: RUDI(INVALID)
		The core has received invalid data whilst receiving/C/ or
		/I/ ordered set. See “status_vector[4:0] signals” in
		Chapter 5 for more information.

1.These signals are synchronous to the core’s internal 125 MHz reference clock. This is userclk2 when the core is used with the RocketIO transceiver; this is gtx_clk when the core is used with TBI.

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

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UG155 March 24, 2008

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Xilinx 1000BASE-X manual Common Signal Pinout, 2Other Common Signals Direction Description

Contents

UG155 March 24 LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SgmiiDate Doc Revision Version Revision HistoryTable of Contents Using the Client-side Gmii Data Path Configuration and Status Interfacing to Other Cores Appendix C Calculating the DCM Fixed Phase Shift Value UG155 March 24 Schedule of Figures 1Functional Block Diagram Using RocketIO TransceiverAuto-Negotiation Typical Application for Dynamic Switching 157 UG155 March 24 Schedule of Tables 5Optional Auto-Negotiation Interface Signal Pinout33SGMII Auto-Negotiation Advertisement Register 4 About This Guide Guide ContentsTypographical ConventionsPreface About This Guide Convention Meaning or Use ExampleConventions Meaning or Use Example Online DocumentPreface About This Guide Introduction Designs Using RocketIO TransceiversAbout the Core Recommended Design ExperienceTechnical Support Additional Core ResourcesFeedback Ethernet 1000BASE-X PCS/PMA or Sgmii CoreFeedback DocumentIntroduction System Overview Core ArchitecturePCS Transmit Engine Gmii BlockPCS Receive Engine and Synchronization Optional Auto-Negotiation BlockOptional PCS Management Registers Ethernet 1000BASE-X PCS/PMA or Sgmii with Ten-Bit-InterfaceRocketIO Interface Block System Overview8B/10B Encoder Core Interfaces8B/10B Decoder Receiver Elastic BufferCore Interfaces Core Architecture Core Interfaces Core Architecture Gmii Pinout Client Side InterfaceEthernet 1000BASE-X PCS/PMA or Sgmii 2Other Common Signals Direction Description Common Signal PinoutMAC Mdio Management Interface Pinout OptionalConfiguration Vector Optional Auto-Negotiation Signal Pinout5Optional Auto-Negotiation Interface Signal Pinout Physical Side Interface Dynamic Switching Signal PinoutEthernet 1000BASE-X PCS/PMA or Sgmii 1000BASE-X PCS with TBI Pinout Generating and Customizing the Core GUI InterfaceComponent Name Select Standard Core FunctionalityGenerating and Customizing the Core Physical Interface SGMII/Dynamic Standard Switching Elastic Buffer OptionsMdio Management Interface Auto-Negotiation3SGMII/Dynamic Standard Switching Options Screen RocketIO Tile Configuration Parameter Values in the XCO FileParameter Values in the XCO File TBI Output GenerationDesign Overview Designing with the CoreDesigning with the Core Design Overview 1000BASE-X Standard with TBI Example DesignExample Design Performing the Sgmii Standard Sgmii Standard Using a RocketIO Transceiver Example Design4Example Design Performing the Sgmii Standard Sgmii Standard with TBI Transceiver Example DesignDesign Guidelines Generate the CoreExamine the Example Design Provided with the Core Synthesize your Design Write an HDL ApplicationCreate a Bitstream Simulate and Download your DesignKeep it Registered Recognize Timing Critical SignalsUse Supported Design Flows Make Only Allowed ModificationsUsing the Client-side Gmii Data Path Gmii TransmissionNormal Frame Transmission Using the Client-side Gmii Data Path Error PropagationGmii Reception Normal Frame ReceptionNormal Frame Reception with Extension Field Frame Reception with ErrorsFalse Carrier Statusvector40 signalsBit0 Link Status Bit1 Link SynchronizationGmii Transmission Bits42 Code Group Reception IndicatorsGmii Reception Overview Designing with Client-side Gmii for the Sgmii StandardGigabit per Second Frame Transmission Megabit per Second Frame TransmissionMegabit per Second Frame Reception Gigabit per Second Frame ReceptionUsing the Gmii as an Internal Connection Using the Gmii as an Internal ConnectionImplementing External Gmii Gmii Transmitter Logic14GMII Transmitter Logic Virtex-II Pro and Virtex-II DevicesImplementing External Gmii Spartan-3, Spartan-3E and Spartan-3A Devices16External Gmii Transmitter Logic for Virtex-4 Devices Virtex-4 Devices17External Gmii Transmitter Logic for Virtex-5 Devices Virtex-5 DevicesGmii Receiver Logic 18External Gmii Receiver Logic Using the Client-side Gmii Data Path Ten-Bit Interface Ten-Bit-Interface LogicTransmitter Logic Receiver Logic Virtex-II and Virtex-II Pro DevicesTen-Bit Interface 2Ten-Bit-Interface Receiver Logic Ten-Bit-Interface LogicComponentnameblock Block Level from example design Method Idelay Iodelay IOB Logic Ibufg 7Alternate Ten-Bit Interface Receiver Logic Virtex-5 Devices Clock Sharing across Multiple Cores with TBI Clock Sharing across Multiple Cores with TBITen-Bit Interface 1000BASE-X with RocketIO Transceivers RocketIO Transceiver LogicVirtex-II Pro Devices 11000BASE-X Connection to a Virtex-II Pro MGT 1000BASE-X with RocketIO TransceiversRocketIO Transceiver Logic Virtex-4 FX Devices21000BASE-X Connection to Virtex-4 MGT Virtex-5 RocketIO GTP Wizard Virtex-5 LXT and SXT Devices31000BASE-X Connection to Virtex-5 GTP Transceivers Virtex-5 RocketIO GTX Wizard Virtex-5 FXT Devices41000BASE-X Connection to Virtex-5 GTX Transceivers Clock Sharing Across Multiple Cores with RocketIO Clock Sharing Across Multiple Cores with RocketIOVirtex-4 FX Devices Componentname block Virtex-5 LXT and SXT Devices Ibufgds Virtex-5 FXT Devices DCM 1000BASE-X with RocketIO Transceivers Selecting the Buffer Implementation from the GUI Receiver Elastic Buffer ImplementationsAnalysis Requirement for the Fpga Fabric Rx Elastic BufferReceiver Elastic Buffer Implementations RocketIO Rx Elastic BufferClosely Related Clock Sources RocketIO Logic using the RocketIO Rx Elastic BufferRocketIO Logic with the Fabric Rx Elastic Buffer RocketIO Logic with the Fabric Rx Elastic Buffer3SGMII Connection to a Virtex-II Pro RocketIO Transceiver Virtex-4 Devices for Sgmii or Dynamic Standards Switching 4SGMII Connection to a Virtex-4 MGT Ethernet 1000BASE-X PCS/PMA or Sgmii 103 5SGMII Connection to a Virtex-5 RocketIO GTP Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 105 6SGMII Connection to a Virtex-5 RocketIO GTX Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 107 108 Ethernet 1000BASE-X PCS/PMA or Sgmii 109 Sgmii Ethernet 1000BASE-X PCS/PMA or Sgmii 111 112 Ethernet 1000BASE-X PCS/PMA or Sgmii 113 114 Configuration and Status Mdio Management InterfaceMdio Bus System Configuration and Status Mdio Transactions1Abbreviations and Terms Write Transaction Mdio AddressingRead Transaction Mdio Management Interface 1Abbreviations and TermsConnecting the Mdio to an External STA Connecting the Mdio to an Internally Integrated STAManagement Registers 1000BASE-X Standard Using the Optional Auto-NegotiationManagement Registers 2MDIO Registers for 1000BASE-X with Auto-NegotiationRegister 0 Control Register Mdio Register 0 Control Register3Control Register Register LSB Management Registers 3Control Register RegisterRegister 1 Status Register Mdio Register 1 Status Register4Status Register Register Registers 2 and 3 PHY Identifiers Management Registers 4Status Register RegisterRegisters 2 and 3 PHY Identifiers Register 4 Auto-Negotiation Advertisement Configuration and Status 5PHY Identifier Registers 2Mdio Register 4 Auto-Negotiation Advertisement Auto-Negotiation Advertisement Register RegisterMdio Register 5 Auto-Negotiation Link Partner Base Register 5 Auto-Negotiation Link Partner BaseRegister 7 Next Page Transmit Register 6 Auto-Negotiation ExpansionMdio Register 6 Auto-Negotiation Expansion 8Auto-Negotiation Expansion Register RegisterRegister 8 Next Page Receive Mdio Register 8 Next Page Receive10Auto-Negotiation Next Page Receive Register Register 15 Extended Status Mdio Register 15 Extended Status Register11Extended Status Register Register 13MDIO Registers for 1000BASE-X without Auto-Negotiation 1000BASE-X Standard Without the Optional Auto-Negotiation14Control Register Register 15Status Register Register Management Registers 14Control Register RegisterConfiguration and Status 15Status Register Register Mdio Registers 2 and 3 PHY Identifier Registers 2 and 3 Phy Identifier16PHY Identifier Registers 2 Mdio Register 15 Extended StatusConfiguration and Status 17Extended Status Register Register 0 Sgmii Control Sgmii Standard Using the Optional Auto-Negotiation18MDIO Registers for 1000BASE-X with Auto-Negotiation Mdio Register 0 Sgmii ControlConfiguration and Status 19SGMII Control Register Management Registers 19SGMII Control Register Register 1 Sgmii StatusMdio Register 1 Sgmii Status 20SGMII Status RegisterConfiguration and Status 20SGMII Status Register 21PHY Identifier Registers 2 Register 4 Sgmii Auto-Negotiation AdvertisementMdio Register 4 Sgmii Auto-Negotiation Advertisement 22SGMII Auto-Negotiation Advertisement RegisterMdio Register 5 Sgmii Auto-Negotiation Link Partner Ability Register 5 Sgmii Auto-Negotiation Link Partner AbilityRegister 7 Sgmii Auto-Negotiation Next Page Transmit Register 6 Sgmii Auto-Negotiation ExpansionRegister 8 Sgmii Next Page Receive Mdio Register 8 Sgmii Next Page Receive26SGMII Auto-Negotiation Next Page Receive Register Register 15 Sgmii Extended Status Mdio Register 15 Sgmii Extended Status27SGMII Extended Status Register Register Register 16 Sgmii Auto-Negotiation Interrupt Control Mdio Register 16 Sgmii Auto-Negotiation Interrupt Control28SGMII Auto-Negotiation Interrupt Control Register 29MDIO Registers for 1000BASE-X with Auto-Negotiation Sgmii Standard without the Optional Auto-NegotiationConfiguration and Status 30SGMII Control Register 31SGMII Status Register Management Registers 30SGMII Control RegisterConfiguration and Status 31SGMII Status Register 33SGMII Auto-Negotiation Advertisement Register 32PHY Identifier Registers 234SGMII Extended Status Register Register Both 1000BASE-X and Sgmii StandardsOptional Configuration Vector Optional Configuration VectorRegister 17 Vendor-specific Standard Selection Register Signal Direction Clock Description Domain 36Optional Configuration and Status VectorsOverview of Operation Auto-NegotiationAuto-Negotiation Sgmii Standard Overview of OperationSgmii Auto-Negotiation Using the Auto-Negotiation Interrupt Setting the Configurable Link Timer1000BASE-X Standard Simulating Auto-NegotiationTypical Application Dynamic Switching of 1000BASE-X and Sgmii StandardsSwitching the Standard Using Mdio Selecting the Power-On / Reset StandardSetting the Auto-Negotiation Link Timer Operation of the CoreOperation of the Core 160 Required Constraints Constraining the CoreMGT Transceiver Placement Constraints Setting MGT AttributesClock Period Constraints Constraining the Core# Enmcommaalign Required Constraints1Local Clock Place and Route for Top MGT Virtex-4 RocketIO MGTs for 1000BASE-X ConstraintsMGT Placement Constraints Setting MGT Transceiver AttributesSetting GTP Transceiver Attributes Ethernet 1000BASE-X PCS/PMA or Sgmii 167 UG155 March 24 Ten-Bit Interface Constraints Setting GTX Transceiver AttributesTen-Bit Interface IOB Constraints 1Input TBI Timing Symbol Min Max Units TBI Input Setup/Hold TimingVirtex-4 Devices Virtex-5 Devices Constraints When Implementing an External GmiiGmii IOB Constraints 2Input Gmii Timing Symbol Min Max Units Gmii Input Setup/Hold TimingEthernet 1000BASE-X PCS/PMA or Sgmii 175 Understanding Timing Reports for Setup/Hold Timing Devices Other Than Virtex-4 or Virtex-5Virtex-4 or Virtex-5 Devices 4Timing Report Setup/Hold Illustration 178 Integrating with the 1-Gigabit Ethernet MAC Core Interfacing to Other CoresMAC Interfacing to Other CoresIntegrating with the 1-Gigabit Ethernet MAC Core Virtex-II Pro Devices182 GTP Virtex-5 LXT and SXT DevicesClkdv Virtex-5 FXT DevicesIntegrating with the Tri-Mode Ethernet MAC Core Integrating with the Tri-Mode Ethernet MAC Core186 IOB Logic 188 Ethernet 1000BASE-X PCS/PMA or Sgmii 189 190 8Tri-Speed Ethernet MAC Extended to Use an Sgmii in Virtex-4 192 Ethernet 1000BASE-X PCS/PMA or Sgmii 193 194 Ethernet 1000BASE-X PCS/PMA or Sgmii 195 196 Special Design Considerations Power ManagementStartup Sequencing LoopbackSpecial Design Considerations Core with RocketIO TransceiverLoopback 200 Implementing the Design Using the Simulation ModelPre-implementation Simulation SynthesisXST Verilog ImplementationGenerating the Xilinx Netlist Mapping the DesignPost-Implementation Simulation Using the ModelStatic Timing Analysis Generating a BitstreamVirtex-5 Devices Other Implementation InformationVerification Core Verification, Compliance, and InteroperabilitySimulation Hardware Verification206 Core Latency Core LatencyLatency for 1000BASE-X PCS with TBI Transmit Path LatencyLatency for Sgmii Calculating the DCM Fixed Phase Shift Value Requirement for DCM Phase ShiftingFinding the Ideal Phase Shift Value for Your System Appendix C Calculating the DCM Fixed Phase Shift Value Introduction 1000BASE-X State MachinesStart of Frame Encoding Even Transmission CaseAppendix D 1000BASE-X State Machines Reception of the Even Case Odd Transmission CaseStart of Frame Encoding Reception of the Odd Case End of Frame Encoding Preamble ShrinkageEnd of Frame Encoding 216 Ethernet 1000BASE-X PCS/PMA or Sgmii 217 218 Rx Elastic Buffer Specifications Rx Elastic Buffers Depths and Maximum Frame SizesRocketIO Rx Elastic Buffers Virtex-II Pro and Virtex-5 Devices Appendix E Rx Elastic Buffer SpecificationsRx Elastic Buffers Depths and Maximum Frame Sizes Virtex-4 FXFigure E-2Elastic Buffer Size for all RocketIO families Sgmii Fabric Rx Elastic BufferFor Sgmii / Dynamic Switching TBI Rx Elastic BufferFor 1000BASE-X Idle Character Removal at 1Gbps 1000BASE-X and Sgmii Clock CorrectionIdle Character Removal at 100 Mbps Sgmii Idle Character Removal at 10 Mbps SgmiiClock Correction Maximum Frame Sizes for Sustained Frame Reception Jumbo Frame ReceptionRocketIO Sgmii Fabric Buffer Problems with Data Reception or Transmission Problems with the MdioDebugging Guide General ChecksProblems with Auto-Negotiation Problems in Obtaining a Link Auto-Negotiation DisabledAppendix F Debugging Guide Symptoms Problems with a High Bit Error RateProblems with a High Bit Error Rate DebuggingRocketIO Transceiver Specific Checks