RocketIO Logic with the Fabric Rx Elastic Buffer
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RocketIO Logic with the Fabric Rx Elastic Buffer
The example design delivered with the core is split between two hierarchical layers, as illustrated in Figure
•Instantiates the core from HDL
•Connects the
The logic implemented in the block level is illustrated in all figures throughout the remainder of this chapter.
Virtex-II Pro Devices
The core is designed for connection to a
Some modifications may be made to the MGT. For example, REFCLK may be used instead of BREFCLK. See the
Figure 8-3 shows that the Rx Elastic Buffer is implemented in the FPGA fabric between the MGT transceiver and the core. This replaces the Rx Elastic Buffer in the MGT (which is bypassed).
This alternative Receiver Elastic Buffer uses a single block RAM to create a buffer twice as large as the one present in the MGT. It is able to cope with larger frame sizes before clock tolerances accumulate and result in emptying or filling of the buffer. This is necessary to guarantee SGMII operation at 10 Mbps, where each frame size is effectively 100 times larger than the same frame would be at 1 Gbps because each byte is repeated 100 times (see “Designing with Client-side GMII for the SGMII Standard,” page 59).
In bypassing the MGT Rx Elastic Buffer, data is clocked out of the MGT synchronously to rxrecclk. This must be placed on constrained local clock routing for reliable operation. See “Virtex-II Pro RocketIO MGTs for SGMII or Dynamic Standards Switching Constraints,” page 163 for constraint details. This methodology is also described in XAPP763.
Note: The brefclk differential pair applied to the MGT is of frequency 62.5 MHz.
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