R
Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers
the device. For more information, see the
brefclkp IBUFGDS IPAD
IPAD brefclkn
brefclk (62.5MHz)
DCM |
| BUFG |
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CLKIN | CLK0 | userclk (62.5 MHz) |
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FB CLK2X180 | userclk2 |
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(125 MHz) |
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| BUFG |
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component_name_block |
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(Block Level) |
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| GT_CUSTOM | ||
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Ethernet |
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| BREFCLK | ||
| PCS/PMA or |
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| TXUSRCLK | ||
| SGMII core |
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| TXUSRCLK2 | ||
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| userclk | FPGA | local |
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| fabric | RXUSRCLK | ||
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| userclk2 | Rx | clock | |
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| Elastic | routing | RXUSRCLK2 |
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| RXRECCLK | ||
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| Buffer |
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component_name_block |
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(Block Level) |
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| GT_CUSTOM | ||
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Ethernet |
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| BREFCLK | ||
| PCS/PMA or |
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| SGMII core |
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| TXUSRCLK | |
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| userclk |
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| TXUSRCLK2 | |
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| userclk2 |
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| FPGA |
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| local |
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| fabric | RXUSRCLK | |
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| Rx | clock | |
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| RXUSRCLK2 | ||
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| Elastic | routing | |
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| Buffer | RXRECCLK | |
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Figure 8-7: Clock Management with Multiple Core Instances with Virtex-II Pro
RocketIO Transceivers for SGMII
108 | www.xilinx.com | Ethernet |
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| UG155 March 24, 2008 |