Xilinx 1000BASE-X manual Schedule of Tables, 5Optional Auto-Negotiation Interface Signal Pinout

Models: 1000BASE-X

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Schedule of Tables

Chapter 2: Core Architecture

Table 2-1:GMII Interface Signal Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 2-2:Other Common Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 2-3:Optional MDIO Interface Signal Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 2-4:Optional Configuration and Status Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 2-5:Optional Auto-Negotiation Interface Signal Pinout. . . . . . . . . . . . . . . . . . . . . . 35

Table 2-6:Optional Dynamic Standard Switching Signals . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 2-7:Optional RocketIO Transceiver Interface Pinout . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 2-8:Optional TBI Interface Signal Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Chapter 3: Generating and Customizing the Core

Table 3-1:XCO File Values and Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Chapter 4: Designing with the Core

 

Table 4-1:Degree of Difficulty for Various Implementations

. 51

Chapter 9: Configuration and Status

 

Table 9-1:Abbreviations and Terms

116

Table 9-2:MDIO Registers for 1000BASE-X with Auto-Negotiation

119

Table 9-3:Control Register (Register 0)

120

Table 9-4:Status Register (Register 1)

122

Table 9-5:PHY Identifier (Registers 2 and 3)

124

Table 9-6:Auto-Negotiation Advertisement Register (Register 4)

124

Table 9-7:Auto-Negotiation Link Partner Ability Base Register (Register 5)

125

Table 9-8:Auto-Negotiation Expansion Register (Register 6)

126

Table 9-9:Auto-Negotiation Next Page Transmit (Register 7)

127

Table 9-10:Auto-Negotiation Next Page Receive (Register 8)

128

Table 9-11:Extended Status Register (Register 15)

128

Table 9-12:Vendor Specific Register: Auto-Negotiation Interrupt

 

Control Register (Register 16)

129

Table 9-13:MDIO Registers for 1000BASE-X without Auto-Negotiation

130

Table 9-14:Control Register (Register 0)

130

Table 9-15:Status Register (Register 1)

132

Table 9-16:PHY Identifier (Registers 2 and 3)

133

Table 9-17:Extended Status (Register 15)

134

Table 9-18:MDIO Registers for 1000BASE-X with Auto-Negotiation

135

Table 9-19:SGMII Control (Register 0)

136

Table 9-20:SGMII Status (Register 1)

137

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

www.xilinx.com

UG155 March 24, 2008

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Xilinx 1000BASE-X manual Schedule of Tables, 5Optional Auto-Negotiation Interface Signal Pinout