4Timing Report Setup/Hold Illustration | Xilinx 1000BASE-X specification

Required Constraints

R

GMII_TX_CLK

Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)

Setup/Hold to		clock gmii_tx_clk
------------	+	------------+	------------+------------------	+	--------	+
		Setup to	Hold to	Clock
Source		clk (edge) clk (edge) Internal Clock(s)		Phase
------------	+	------------+	------------+------------------	+	--------	+
gmii_tx_en		-6.501(R)	7.875(R)gmii_tx_clk_bufg		0.000
gmii_tx_er		-6.504(R)	7.878(R)gmii_tx_clk_bufg		0.000
gmii_txd<0>		-6.506(R)	7.880(R)gmii_tx_clk_bufg		0.000
gmii_txd<1>		-6.521(R)	7.893(R)gmii_tx_clk_bufg		0.000
gmii_txd<2>		-6.518(R)	7.890(R)gmii_tx_clk_bufg		0.000
gmii_txd<3>		-6.515(R)	7.889(R)gmii_tx_clk_bufg		0.000
gmii_txd<4>		-6.521(R)	7.894(R)gmii_tx_clk_bufg		0.000
gmii_txd<5>		-6.520(R)	7.895(R)gmii_tx_clk_bufg		0.000
gmii_txd<6>		-6.514(R)	7.889(R)gmii_tx_clk_bufg		0.000
gmii_txd<7>		-6.513(R)	7.889(R)gmii_tx_clk_bufg		0.000
------------	+	------------+	------------+------------------	+	--------	+

The implementation requires -6.501 ns of setup. Figure 12-4illustrates that this represents a figure of 1.499 ns relative to the following rising edge of the clock (because the IDELAY has acted to delay the clock by an entire period when measured from the input flip-flop). This is less than the 2 ns required, and so there is slack.

The implementation requires 7.893 ns of hold. Figure 12-4illustrates that this represents a figure of -0.107 ns relative to the following rising edge of the clock (because the IDELAY has acted to delay the clock by an entire period when measured from the input flip-flop). This is less than the 0 ns required, and so there is slack.

GMII_TXD[7:0], GMII_TX_EN, GMII_TX_ER

8 ns

-6.501 ns

					tHOLD = 7.893 - 8
					tHOLD = 7.893 - 8
						= -0.107 ns
7.893 ns						= -0.107 ns

tSETUP = 8 - 6.501 = 1.499 ns

8 ns

Figure 12-4:Timing Report Setup/Hold Illustration

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

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177

UG155 March 24, 2008

Image 177

Xilinx 1000BASE-X manual 4Timing Report Setup/Hold Illustration

Contents

UG155 March 24 LogiCORE IP Ethernet 1000BASE-X PCS/PMA or Sgmii Date Doc Revision Version Revision History Table of Contents Using the Client-side Gmii Data Path Configuration and Status Interfacing to Other Cores Appendix C Calculating the DCM Fixed Phase Shift Value UG155 March 24 Schedule of Figures 1Functional Block Diagram Using RocketIO Transceiver Auto-Negotiation Typical Application for Dynamic Switching 157 UG155 March 24 Schedule of Tables 5Optional Auto-Negotiation Interface Signal Pinout 33SGMII Auto-Negotiation Advertisement Register 4 About This Guide Guide Contents Typographical ConventionsPreface About This Guide Convention Meaning or Use Example Conventions Meaning or Use Example Online Document Preface About This Guide Introduction Designs Using RocketIO TransceiversAbout the Core Recommended Design Experience Technical Support Additional Core ResourcesFeedback Ethernet 1000BASE-X PCS/PMA or Sgmii Core Feedback Document Introduction System Overview Core Architecture PCS Transmit Engine Gmii BlockPCS Receive Engine and Synchronization Optional Auto-Negotiation Block Optional PCS Management Registers Ethernet 1000BASE-X PCS/PMA or Sgmii with Ten-Bit-InterfaceRocketIO Interface Block System Overview 8B/10B Encoder Core Interfaces8B/10B Decoder Receiver Elastic Buffer Core Interfaces Core Architecture Core Interfaces Core Architecture Gmii Pinout Client Side Interface Ethernet 1000BASE-X PCS/PMA or Sgmii 2Other Common Signals Direction Description Common Signal Pinout MAC Mdio Management Interface Pinout Optional Configuration Vector Optional Auto-Negotiation Signal Pinout5Optional Auto-Negotiation Interface Signal Pinout Physical Side Interface Dynamic Switching Signal Pinout Ethernet 1000BASE-X PCS/PMA or Sgmii 1000BASE-X PCS with TBI Pinout Generating and Customizing the Core GUI InterfaceComponent Name Select Standard Core FunctionalityGenerating and Customizing the Core Physical Interface SGMII/Dynamic Standard Switching Elastic Buffer OptionsMdio Management Interface Auto-Negotiation 3SGMII/Dynamic Standard Switching Options Screen RocketIO Tile Configuration Parameter Values in the XCO FileParameter Values in the XCO File TBI Output Generation Design Overview Designing with the Core Designing with the Core Design Overview 1000BASE-X Standard with TBI Example Design Example Design Performing the Sgmii Standard Sgmii Standard Using a RocketIO Transceiver Example Design 4Example Design Performing the Sgmii Standard Sgmii Standard with TBI Transceiver Example Design Design Guidelines Generate the CoreExamine the Example Design Provided with the Core Synthesize your Design Write an HDL ApplicationCreate a Bitstream Simulate and Download your Design Keep it Registered Recognize Timing Critical SignalsUse Supported Design Flows Make Only Allowed Modifications Using the Client-side Gmii Data Path Gmii TransmissionNormal Frame Transmission Using the Client-side Gmii Data Path Error PropagationGmii Reception Normal Frame Reception Normal Frame Reception with Extension Field Frame Reception with Errors False Carrier Statusvector40 signalsBit0 Link Status Bit1 Link Synchronization Gmii Transmission Bits42 Code Group Reception Indicators Gmii Reception Overview Designing with Client-side Gmii for the Sgmii StandardGigabit per Second Frame Transmission Megabit per Second Frame Transmission Megabit per Second Frame Reception Gigabit per Second Frame Reception Using the Gmii as an Internal Connection Using the Gmii as an Internal ConnectionImplementing External Gmii Gmii Transmitter Logic 14GMII Transmitter Logic Virtex-II Pro and Virtex-II Devices Implementing External Gmii Spartan-3, Spartan-3E and Spartan-3A Devices 16External Gmii Transmitter Logic for Virtex-4 Devices Virtex-4 Devices 17External Gmii Transmitter Logic for Virtex-5 Devices Virtex-5 Devices Gmii Receiver Logic 18External Gmii Receiver Logic Using the Client-side Gmii Data Path Ten-Bit Interface Ten-Bit-Interface LogicTransmitter Logic Receiver Logic Virtex-II and Virtex-II Pro DevicesTen-Bit Interface 2Ten-Bit-Interface Receiver Logic Ten-Bit-Interface Logic Componentnameblock Block Level from example design Method Idelay Iodelay IOB Logic Ibufg 7Alternate Ten-Bit Interface Receiver Logic Virtex-5 Devices Clock Sharing across Multiple Cores with TBI Clock Sharing across Multiple Cores with TBI Ten-Bit Interface 1000BASE-X with RocketIO Transceivers RocketIO Transceiver LogicVirtex-II Pro Devices 11000BASE-X Connection to a Virtex-II Pro MGT 1000BASE-X with RocketIO Transceivers RocketIO Transceiver Logic Virtex-4 FX Devices 21000BASE-X Connection to Virtex-4 MGT Virtex-5 RocketIO GTP Wizard Virtex-5 LXT and SXT Devices 31000BASE-X Connection to Virtex-5 GTP Transceivers Virtex-5 RocketIO GTX Wizard Virtex-5 FXT Devices 41000BASE-X Connection to Virtex-5 GTX Transceivers Clock Sharing Across Multiple Cores with RocketIO Clock Sharing Across Multiple Cores with RocketIO Virtex-4 FX Devices Componentname block Virtex-5 LXT and SXT Devices Ibufgds Virtex-5 FXT Devices DCM 1000BASE-X with RocketIO Transceivers Selecting the Buffer Implementation from the GUI Receiver Elastic Buffer Implementations Analysis Requirement for the Fpga Fabric Rx Elastic Buffer Receiver Elastic Buffer Implementations RocketIO Rx Elastic Buffer Closely Related Clock Sources RocketIO Logic using the RocketIO Rx Elastic Buffer RocketIO Logic with the Fabric Rx Elastic Buffer RocketIO Logic with the Fabric Rx Elastic Buffer 3SGMII Connection to a Virtex-II Pro RocketIO Transceiver Virtex-4 Devices for Sgmii or Dynamic Standards Switching 4SGMII Connection to a Virtex-4 MGT Ethernet 1000BASE-X PCS/PMA or Sgmii 103 5SGMII Connection to a Virtex-5 RocketIO GTP Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 105 6SGMII Connection to a Virtex-5 RocketIO GTX Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 107 108 Ethernet 1000BASE-X PCS/PMA or Sgmii 109 Sgmii Ethernet 1000BASE-X PCS/PMA or Sgmii 111 112 Ethernet 1000BASE-X PCS/PMA or Sgmii 113 114 Configuration and Status Mdio Management InterfaceMdio Bus System Configuration and Status Mdio Transactions1Abbreviations and Terms Write Transaction Mdio AddressingRead Transaction Mdio Management Interface 1Abbreviations and Terms Connecting the Mdio to an External STA Connecting the Mdio to an Internally Integrated STA Management Registers 1000BASE-X Standard Using the Optional Auto-NegotiationManagement Registers 2MDIO Registers for 1000BASE-X with Auto-Negotiation Register 0 Control Register Mdio Register 0 Control Register3Control Register Register LSB Management Registers 3Control Register Register Register 1 Status Register Mdio Register 1 Status Register4Status Register Register Registers 2 and 3 PHY Identifiers Management Registers 4Status Register RegisterRegisters 2 and 3 PHY Identifiers Register 4 Auto-Negotiation Advertisement Configuration and Status 5PHY Identifier Registers 2Mdio Register 4 Auto-Negotiation Advertisement Auto-Negotiation Advertisement Register Register Mdio Register 5 Auto-Negotiation Link Partner Base Register 5 Auto-Negotiation Link Partner Base Register 7 Next Page Transmit Register 6 Auto-Negotiation ExpansionMdio Register 6 Auto-Negotiation Expansion 8Auto-Negotiation Expansion Register Register Register 8 Next Page Receive Mdio Register 8 Next Page Receive10Auto-Negotiation Next Page Receive Register Register 15 Extended Status Mdio Register 15 Extended Status Register11Extended Status Register Register 13MDIO Registers for 1000BASE-X without Auto-Negotiation 1000BASE-X Standard Without the Optional Auto-Negotiation 14Control Register Register 15Status Register Register Management Registers 14Control Register Register Configuration and Status 15Status Register Register Mdio Registers 2 and 3 PHY Identifier Registers 2 and 3 Phy Identifier16PHY Identifier Registers 2 Mdio Register 15 Extended Status Configuration and Status 17Extended Status Register Register 0 Sgmii Control Sgmii Standard Using the Optional Auto-Negotiation18MDIO Registers for 1000BASE-X with Auto-Negotiation Mdio Register 0 Sgmii Control Configuration and Status 19SGMII Control Register Management Registers 19SGMII Control Register Register 1 Sgmii StatusMdio Register 1 Sgmii Status 20SGMII Status Register Configuration and Status 20SGMII Status Register 21PHY Identifier Registers 2 Register 4 Sgmii Auto-Negotiation AdvertisementMdio Register 4 Sgmii Auto-Negotiation Advertisement 22SGMII Auto-Negotiation Advertisement Register Mdio Register 5 Sgmii Auto-Negotiation Link Partner Ability Register 5 Sgmii Auto-Negotiation Link Partner Ability Register 7 Sgmii Auto-Negotiation Next Page Transmit Register 6 Sgmii Auto-Negotiation Expansion Register 8 Sgmii Next Page Receive Mdio Register 8 Sgmii Next Page Receive26SGMII Auto-Negotiation Next Page Receive Register Register 15 Sgmii Extended Status Mdio Register 15 Sgmii Extended Status27SGMII Extended Status Register Register Register 16 Sgmii Auto-Negotiation Interrupt Control Mdio Register 16 Sgmii Auto-Negotiation Interrupt Control28SGMII Auto-Negotiation Interrupt Control Register 29MDIO Registers for 1000BASE-X with Auto-Negotiation Sgmii Standard without the Optional Auto-Negotiation Configuration and Status 30SGMII Control Register 31SGMII Status Register Management Registers 30SGMII Control Register Configuration and Status 31SGMII Status Register 33SGMII Auto-Negotiation Advertisement Register 32PHY Identifier Registers 2 34SGMII Extended Status Register Register Both 1000BASE-X and Sgmii Standards Optional Configuration Vector Optional Configuration VectorRegister 17 Vendor-specific Standard Selection Register Signal Direction Clock Description Domain 36Optional Configuration and Status Vectors Overview of Operation Auto-Negotiation Auto-Negotiation Sgmii Standard Overview of OperationSgmii Auto-Negotiation Using the Auto-Negotiation Interrupt Setting the Configurable Link Timer1000BASE-X Standard Simulating Auto-Negotiation Typical Application Dynamic Switching of 1000BASE-X and Sgmii Standards Switching the Standard Using Mdio Selecting the Power-On / Reset StandardSetting the Auto-Negotiation Link Timer Operation of the Core Operation of the Core 160 Required Constraints Constraining the Core MGT Transceiver Placement Constraints Setting MGT AttributesClock Period Constraints Constraining the Core # Enmcommaalign Required Constraints 1Local Clock Place and Route for Top MGT Virtex-4 RocketIO MGTs for 1000BASE-X Constraints MGT Placement Constraints Setting MGT Transceiver Attributes Setting GTP Transceiver Attributes Ethernet 1000BASE-X PCS/PMA or Sgmii 167 UG155 March 24 Ten-Bit Interface Constraints Setting GTX Transceiver Attributes Ten-Bit Interface IOB Constraints 1Input TBI Timing Symbol Min Max Units TBI Input Setup/Hold Timing Virtex-4 Devices Virtex-5 Devices Constraints When Implementing an External Gmii Gmii IOB Constraints 2Input Gmii Timing Symbol Min Max Units Gmii Input Setup/Hold Timing Ethernet 1000BASE-X PCS/PMA or Sgmii 175 Understanding Timing Reports for Setup/Hold Timing Devices Other Than Virtex-4 or Virtex-5Virtex-4 or Virtex-5 Devices 4Timing Report Setup/Hold Illustration 178 Integrating with the 1-Gigabit Ethernet MAC Core Interfacing to Other Cores MAC Interfacing to Other Cores Integrating with the 1-Gigabit Ethernet MAC Core Virtex-II Pro Devices 182 GTP Virtex-5 LXT and SXT Devices Clkdv Virtex-5 FXT Devices Integrating with the Tri-Mode Ethernet MAC Core Integrating with the Tri-Mode Ethernet MAC Core 186 IOB Logic 188 Ethernet 1000BASE-X PCS/PMA or Sgmii 189 190 8Tri-Speed Ethernet MAC Extended to Use an Sgmii in Virtex-4 192 Ethernet 1000BASE-X PCS/PMA or Sgmii 193 194 Ethernet 1000BASE-X PCS/PMA or Sgmii 195 196 Special Design Considerations Power ManagementStartup Sequencing Loopback Special Design Considerations Core with RocketIO Transceiver Loopback 200 Implementing the Design Using the Simulation ModelPre-implementation Simulation Synthesis XST Verilog ImplementationGenerating the Xilinx Netlist Mapping the Design Post-Implementation Simulation Using the ModelStatic Timing Analysis Generating a Bitstream Virtex-5 Devices Other Implementation Information Verification Core Verification, Compliance, and InteroperabilitySimulation Hardware Verification 206 Core Latency Core LatencyLatency for 1000BASE-X PCS with TBI Transmit Path Latency Latency for Sgmii Calculating the DCM Fixed Phase Shift Value Requirement for DCM Phase ShiftingFinding the Ideal Phase Shift Value for Your System Appendix C Calculating the DCM Fixed Phase Shift Value Introduction 1000BASE-X State Machines Start of Frame Encoding Even Transmission CaseAppendix D 1000BASE-X State Machines Reception of the Even Case Odd Transmission CaseStart of Frame Encoding Reception of the Odd Case End of Frame Encoding Preamble ShrinkageEnd of Frame Encoding 216 Ethernet 1000BASE-X PCS/PMA or Sgmii 217 218 Rx Elastic Buffer Specifications Rx Elastic Buffers Depths and Maximum Frame SizesRocketIO Rx Elastic Buffers Virtex-II Pro and Virtex-5 Devices Appendix E Rx Elastic Buffer Specifications Rx Elastic Buffers Depths and Maximum Frame Sizes Virtex-4 FX Figure E-2Elastic Buffer Size for all RocketIO families Sgmii Fabric Rx Elastic Buffer For Sgmii / Dynamic Switching TBI Rx Elastic BufferFor 1000BASE-X Idle Character Removal at 1Gbps 1000BASE-X and Sgmii Clock Correction Idle Character Removal at 100 Mbps Sgmii Idle Character Removal at 10 Mbps SgmiiClock Correction Maximum Frame Sizes for Sustained Frame Reception Jumbo Frame ReceptionRocketIO Sgmii Fabric Buffer Problems with Data Reception or Transmission Problems with the MdioDebugging Guide General Checks Problems with Auto-Negotiation Problems in Obtaining a Link Auto-Negotiation DisabledAppendix F Debugging Guide Symptoms Problems with a High Bit Error RateProblems with a High Bit Error Rate Debugging RocketIO Transceiver Specific Checks