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Xilinx manual Virtex-4 RocketIO MGTs for 1000BASE-X Constraints

Models: 1000BASE-X

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Chapter 12: Constraining the Core

Legend:

Green - Vertical

Long Line

Orange - VFULLHEX

Red - HFULLHEX

Yellow - BRAM/

Multiplier/Slices/

MGT

Figure 12-1:Local Clock Place and Route for Top MGT

Virtex-4 RocketIO MGTs for 1000BASE-X Constraints

The constraints defined in this section are implemented in the UCF for the example designs delivered with the core. Sections from the UCF are copied into the following descriptions to serve as examples and should be studied in conjunction with the HDL source code for the example design. See also “Virtex-4 FX Devices” in Chapter 7.

Clock Period Constraints

The clock txoutclk is provided by the MGT for use in the FPGA fabric. It is connected to global clock routing to produce the usrclk2 signal. This is the main 125 MHz clock used by all core logic and must be constrained.

DCLK is a clock with a frequency between 25 and 50 MHz, which must be provided to the Dynamic Reconfiguration Port and to the calibration block of the MGT. In the example design, this is constrained to 50 MHz.

164	www.xilinx.com	Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
		UG155 March 24, 2008

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Xilinx manual Virtex-4 RocketIO MGTs for 1000BASE-X Constraints, 1Local Clock Place and Route for Top MGT

Contents

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or Sgmii UG155 March 24Revision History Date Doc Revision VersionTable of Contents Using the Client-side Gmii Data Path Configuration and Status Interfacing to Other Cores Appendix C Calculating the DCM Fixed Phase Shift Value UG155 March 24 1Functional Block Diagram Using RocketIO Transceiver Schedule of FiguresAuto-Negotiation Typical Application for Dynamic Switching 157 UG155 March 24 5Optional Auto-Negotiation Interface Signal Pinout Schedule of Tables33SGMII Auto-Negotiation Advertisement Register 4 Guide Contents About This GuideConventions TypographicalPreface About This Guide Convention Meaning or Use ExampleOnline Document Conventions Meaning or Use ExamplePreface About This Guide Designs Using RocketIO Transceivers IntroductionAbout the Core Recommended Design ExperienceAdditional Core Resources Technical SupportFeedback Ethernet 1000BASE-X PCS/PMA or Sgmii CoreDocument FeedbackIntroduction Core Architecture System OverviewGmii Block PCS Transmit EnginePCS Receive Engine and Synchronization Optional Auto-Negotiation BlockEthernet 1000BASE-X PCS/PMA or Sgmii with Ten-Bit-Interface Optional PCS Management RegistersRocketIO Interface Block System OverviewCore Interfaces 8B/10B Encoder8B/10B Decoder Receiver Elastic BufferCore Interfaces Core Architecture Core Interfaces Core Architecture Client Side Interface Gmii PinoutEthernet 1000BASE-X PCS/PMA or Sgmii Common Signal Pinout 2Other Common Signals Direction DescriptionMdio Management Interface Pinout Optional MAC5Optional Auto-Negotiation Interface Signal Pinout Configuration Vector OptionalAuto-Negotiation Signal Pinout Dynamic Switching Signal Pinout Physical Side InterfaceEthernet 1000BASE-X PCS/PMA or Sgmii 1000BASE-X PCS with TBI Pinout Component Name Generating and Customizing the CoreGUI Interface Generating and Customizing the Core Select StandardCore Functionality SGMII/Dynamic Standard Switching Elastic Buffer Options Physical InterfaceMdio Management Interface Auto-Negotiation3SGMII/Dynamic Standard Switching Options Screen Parameter Values in the XCO File RocketIO Tile ConfigurationParameter Values in the XCO File Output Generation TBIDesigning with the Core Design OverviewDesigning with the Core 1000BASE-X Standard with TBI Example Design Design OverviewSgmii Standard Using a RocketIO Transceiver Example Design Example Design Performing the Sgmii StandardSgmii Standard with TBI Transceiver Example Design 4Example Design Performing the Sgmii StandardExamine the Example Design Provided with the Core Design GuidelinesGenerate the Core Write an HDL Application Synthesize your DesignCreate a Bitstream Simulate and Download your DesignRecognize Timing Critical Signals Keep it RegisteredUse Supported Design Flows Make Only Allowed ModificationsNormal Frame Transmission Using the Client-side Gmii Data PathGmii Transmission Error Propagation Using the Client-side Gmii Data PathGmii Reception Normal Frame ReceptionFrame Reception with Errors Normal Frame Reception with Extension FieldStatusvector40 signals False CarrierBit0 Link Status Bit1 Link SynchronizationBits42 Code Group Reception Indicators Gmii TransmissionGmii Reception Designing with Client-side Gmii for the Sgmii Standard OverviewGigabit per Second Frame Transmission Megabit per Second Frame TransmissionGigabit per Second Frame Reception Megabit per Second Frame ReceptionUsing the Gmii as an Internal Connection Using the Gmii as an Internal ConnectionImplementing External Gmii Gmii Transmitter LogicVirtex-II Pro and Virtex-II Devices 14GMII Transmitter LogicSpartan-3, Spartan-3E and Spartan-3A Devices Implementing External GmiiVirtex-4 Devices 16External Gmii Transmitter Logic for Virtex-4 DevicesVirtex-5 Devices 17External Gmii Transmitter Logic for Virtex-5 DevicesGmii Receiver Logic 18External Gmii Receiver Logic Using the Client-side Gmii Data Path Transmitter Logic Ten-Bit InterfaceTen-Bit-Interface Logic Ten-Bit Interface Receiver LogicVirtex-II and Virtex-II Pro Devices Ten-Bit-Interface Logic 2Ten-Bit-Interface Receiver LogicComponentnameblock Block Level from example design Method Idelay Iodelay IOB Logic Ibufg 7Alternate Ten-Bit Interface Receiver Logic Virtex-5 Devices Clock Sharing across Multiple Cores with TBI Clock Sharing across Multiple Cores with TBITen-Bit Interface Virtex-II Pro Devices 1000BASE-X with RocketIO TransceiversRocketIO Transceiver Logic 1000BASE-X with RocketIO Transceivers 11000BASE-X Connection to a Virtex-II Pro MGTVirtex-4 FX Devices RocketIO Transceiver Logic21000BASE-X Connection to Virtex-4 MGT Virtex-5 LXT and SXT Devices Virtex-5 RocketIO GTP Wizard31000BASE-X Connection to Virtex-5 GTP Transceivers Virtex-5 FXT Devices Virtex-5 RocketIO GTX Wizard41000BASE-X Connection to Virtex-5 GTX Transceivers Clock Sharing Across Multiple Cores with RocketIO Clock Sharing Across Multiple Cores with RocketIOVirtex-4 FX Devices Componentname block Virtex-5 LXT and SXT Devices Ibufgds Virtex-5 FXT Devices DCM 1000BASE-X with RocketIO Transceivers Receiver Elastic Buffer Implementations Selecting the Buffer Implementation from the GUIRequirement for the Fpga Fabric Rx Elastic Buffer AnalysisRocketIO Rx Elastic Buffer Receiver Elastic Buffer ImplementationsRocketIO Logic using the RocketIO Rx Elastic Buffer Closely Related Clock SourcesRocketIO Logic with the Fabric Rx Elastic Buffer RocketIO Logic with the Fabric Rx Elastic Buffer3SGMII Connection to a Virtex-II Pro RocketIO Transceiver Virtex-4 Devices for Sgmii or Dynamic Standards Switching 4SGMII Connection to a Virtex-4 MGT Ethernet 1000BASE-X PCS/PMA or Sgmii 103 5SGMII Connection to a Virtex-5 RocketIO GTP Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 105 6SGMII Connection to a Virtex-5 RocketIO GTX Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 107 108 Ethernet 1000BASE-X PCS/PMA or Sgmii 109 Sgmii Ethernet 1000BASE-X PCS/PMA or Sgmii 111 112 Ethernet 1000BASE-X PCS/PMA or Sgmii 113 114 Mdio Bus System Configuration and StatusMdio Management Interface 1Abbreviations and Terms Configuration and StatusMdio Transactions Mdio Addressing Write TransactionRead Transaction Mdio Management Interface 1Abbreviations and TermsConnecting the Mdio to an Internally Integrated STA Connecting the Mdio to an External STA1000BASE-X Standard Using the Optional Auto-Negotiation Management RegistersManagement Registers 2MDIO Registers for 1000BASE-X with Auto-Negotiation3Control Register Register Register 0 Control RegisterMdio Register 0 Control Register Management Registers 3Control Register Register LSB4Status Register Register Register 1 Status RegisterMdio Register 1 Status Register Registers 2 and 3 PHY Identifiers Registers 2 and 3 PHY IdentifiersManagement Registers 4Status Register Register Configuration and Status 5PHY Identifier Registers 2 Register 4 Auto-Negotiation AdvertisementMdio Register 4 Auto-Negotiation Advertisement Auto-Negotiation Advertisement Register RegisterRegister 5 Auto-Negotiation Link Partner Base Mdio Register 5 Auto-Negotiation Link Partner BaseRegister 6 Auto-Negotiation Expansion Register 7 Next Page TransmitMdio Register 6 Auto-Negotiation Expansion 8Auto-Negotiation Expansion Register Register10Auto-Negotiation Next Page Receive Register Register 8 Next Page ReceiveMdio Register 8 Next Page Receive 11Extended Status Register Register Register 15 Extended StatusMdio Register 15 Extended Status Register 1000BASE-X Standard Without the Optional Auto-Negotiation 13MDIO Registers for 1000BASE-X without Auto-Negotiation14Control Register Register Management Registers 14Control Register Register 15Status Register RegisterConfiguration and Status 15Status Register Register Registers 2 and 3 Phy Identifier Mdio Registers 2 and 3 PHY Identifier16PHY Identifier Registers 2 Mdio Register 15 Extended StatusConfiguration and Status 17Extended Status Register Sgmii Standard Using the Optional Auto-Negotiation Register 0 Sgmii Control18MDIO Registers for 1000BASE-X with Auto-Negotiation Mdio Register 0 Sgmii ControlConfiguration and Status 19SGMII Control Register Register 1 Sgmii Status Management Registers 19SGMII Control RegisterMdio Register 1 Sgmii Status 20SGMII Status RegisterConfiguration and Status 20SGMII Status Register Register 4 Sgmii Auto-Negotiation Advertisement 21PHY Identifier Registers 2Mdio Register 4 Sgmii Auto-Negotiation Advertisement 22SGMII Auto-Negotiation Advertisement RegisterRegister 5 Sgmii Auto-Negotiation Link Partner Ability Mdio Register 5 Sgmii Auto-Negotiation Link Partner AbilityRegister 6 Sgmii Auto-Negotiation Expansion Register 7 Sgmii Auto-Negotiation Next Page Transmit26SGMII Auto-Negotiation Next Page Receive Register Register 8 Sgmii Next Page ReceiveMdio Register 8 Sgmii Next Page Receive 27SGMII Extended Status Register Register Register 15 Sgmii Extended StatusMdio Register 15 Sgmii Extended Status 28SGMII Auto-Negotiation Interrupt Control Register Register 16 Sgmii Auto-Negotiation Interrupt ControlMdio Register 16 Sgmii Auto-Negotiation Interrupt Control Sgmii Standard without the Optional Auto-Negotiation 29MDIO Registers for 1000BASE-X with Auto-NegotiationConfiguration and Status 30SGMII Control Register Management Registers 30SGMII Control Register 31SGMII Status RegisterConfiguration and Status 31SGMII Status Register 32PHY Identifier Registers 2 33SGMII Auto-Negotiation Advertisement RegisterBoth 1000BASE-X and Sgmii Standards 34SGMII Extended Status Register RegisterRegister 17 Vendor-specific Standard Selection Register Optional Configuration VectorOptional Configuration Vector 36Optional Configuration and Status Vectors Signal Direction Clock Description DomainAuto-Negotiation Overview of OperationAuto-Negotiation Sgmii Auto-Negotiation Sgmii StandardOverview of Operation Setting the Configurable Link Timer Using the Auto-Negotiation Interrupt1000BASE-X Standard Simulating Auto-NegotiationDynamic Switching of 1000BASE-X and Sgmii Standards Typical ApplicationSelecting the Power-On / Reset Standard Switching the Standard Using MdioSetting the Auto-Negotiation Link Timer Operation of the CoreOperation of the Core 160 Constraining the Core Required ConstraintsSetting MGT Attributes MGT Transceiver Placement ConstraintsClock Period Constraints Constraining the CoreRequired Constraints # EnmcommaalignVirtex-4 RocketIO MGTs for 1000BASE-X Constraints 1Local Clock Place and Route for Top MGTSetting MGT Transceiver Attributes MGT Placement ConstraintsSetting GTP Transceiver Attributes Ethernet 1000BASE-X PCS/PMA or Sgmii 167 UG155 March 24 Setting GTX Transceiver Attributes Ten-Bit Interface ConstraintsTen-Bit Interface IOB Constraints TBI Input Setup/Hold Timing 1Input TBI Timing Symbol Min Max UnitsVirtex-4 Devices Constraints When Implementing an External Gmii Virtex-5 DevicesGmii IOB Constraints Gmii Input Setup/Hold Timing 2Input Gmii Timing Symbol Min Max UnitsEthernet 1000BASE-X PCS/PMA or Sgmii 175 Virtex-4 or Virtex-5 Devices Understanding Timing Reports for Setup/Hold TimingDevices Other Than Virtex-4 or Virtex-5 4Timing Report Setup/Hold Illustration 178 Interfacing to Other Cores Integrating with the 1-Gigabit Ethernet MAC CoreInterfacing to Other Cores MACVirtex-II Pro Devices Integrating with the 1-Gigabit Ethernet MAC Core182 Virtex-5 LXT and SXT Devices GTPVirtex-5 FXT Devices ClkdvIntegrating with the Tri-Mode Ethernet MAC Core Integrating with the Tri-Mode Ethernet MAC Core186 IOB Logic 188 Ethernet 1000BASE-X PCS/PMA or Sgmii 189 190 8Tri-Speed Ethernet MAC Extended to Use an Sgmii in Virtex-4 192 Ethernet 1000BASE-X PCS/PMA or Sgmii 193 194 Ethernet 1000BASE-X PCS/PMA or Sgmii 195 196 Power Management Special Design ConsiderationsStartup Sequencing LoopbackCore with RocketIO Transceiver Special Design ConsiderationsLoopback 200 Using the Simulation Model Implementing the DesignPre-implementation Simulation SynthesisImplementation XST VerilogGenerating the Xilinx Netlist Mapping the DesignUsing the Model Post-Implementation SimulationStatic Timing Analysis Generating a BitstreamOther Implementation Information Virtex-5 DevicesCore Verification, Compliance, and Interoperability VerificationSimulation Hardware Verification206 Core Latency Core LatencyLatency for 1000BASE-X PCS with TBI Transmit Path LatencyLatency for Sgmii Finding the Ideal Phase Shift Value for Your System Calculating the DCM Fixed Phase Shift ValueRequirement for DCM Phase Shifting Appendix C Calculating the DCM Fixed Phase Shift Value 1000BASE-X State Machines IntroductionAppendix D 1000BASE-X State Machines Start of Frame EncodingEven Transmission Case Start of Frame Encoding Reception of the Even CaseOdd Transmission Case Reception of the Odd Case End of Frame Encoding End of Frame EncodingPreamble Shrinkage 216 Ethernet 1000BASE-X PCS/PMA or Sgmii 217 218 RocketIO Rx Elastic Buffers Rx Elastic Buffer SpecificationsRx Elastic Buffers Depths and Maximum Frame Sizes Appendix E Rx Elastic Buffer Specifications Virtex-II Pro and Virtex-5 DevicesVirtex-4 FX Rx Elastic Buffers Depths and Maximum Frame SizesSgmii Fabric Rx Elastic Buffer Figure E-2Elastic Buffer Size for all RocketIO familiesFor 1000BASE-X For Sgmii / Dynamic SwitchingTBI Rx Elastic Buffer Clock Correction Idle Character Removal at 1Gbps 1000BASE-X and SgmiiClock Correction Idle Character Removal at 100 Mbps SgmiiIdle Character Removal at 10 Mbps Sgmii RocketIO Sgmii Fabric Buffer Maximum Frame Sizes for Sustained Frame ReceptionJumbo Frame Reception Problems with the Mdio Problems with Data Reception or TransmissionDebugging Guide General ChecksAppendix F Debugging Guide Problems with Auto-NegotiationProblems in Obtaining a Link Auto-Negotiation Disabled Problems with a High Bit Error Rate SymptomsProblems with a High Bit Error Rate DebuggingRocketIO Transceiver Specific Checks